Semiconductor package, semiconductor device and method for packaging semiconductor device

Patent metadata

Field	Value
Publication number	US-10867882-B2
Application number	US-201916693386-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Jun 25, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first conductive wire layer with a first mounting area and a second mounting area, wherein the first mounting area and the second mounting area do not overlap;
an integrated circuit (IC) disposed on a first surface of the first mounting area, wherein the IC is electrically insulated from the first conductive wire layer;
a radiation fin structure, disposed on a second surface of the first mounting area; and
an antenna, disposed on the second mounting area.

2. The semiconductor package of claim 1 , wherein the antenna is disposed on a surface of the second mounting area, and the second surface of the first mounting area and the surface of the second mounting area are in the same plane.

3. The semiconductor package of claim 1 , wherein the antenna is disposed side-by-side to the heat dissipation structure.

4. The semiconductor package of claim 1 , further comprising:
a first thermal paste layer, disposed between the IC and the second surface of the first conductive wire layer to form a heat dissipation path from the IC to the radiation fin structure through the first conductive wire layer, wherein the first thermal paste layer is formed by thermally conductive and electrically insulated material.

5. The semiconductor package of claim 1 , wherein the antenna comprises at least one first antenna patch, and the at least one first antenna patch is formed in the first conductive wire layer.

6. The semiconductor package of claim 1 , further comprising:
a dielectric layer, formed on the second surface of the first conductive wire layer; and
at least one second antenna patch of the antenna, formed on the dielectric layer.

7. The semiconductor package of claim 6 , wherein the dielectric layer comprises an air cavity that is disposed side-by-side to the heat dissipation structure.

8. The semiconductor package of claim 1 , further comprising:
a second conductive wire layer, disposed between a substrate and the first conductive wire layer, wherein the second conductive wire layer contacts the first conductive wire layer, and the radiation fin structure is mounted to the second surface of the first conductive wire layer through the second conductive wire layer.

9. The semiconductor package of claim 1 , further comprising:
a second thermal paste layer, disposed between the heat dissipation structure and a second conductive wire layer.

10. The semiconductor package of claim 1 , further comprising:
a molding layer, disposed over the first surface of the first conductive wire layer;
a third conductive wire layer, disposed on the molding layer and the IC; and
at least one solder ball, disposed on the third conductive wire layer to electrically connect to the IC with the at least one clout solder ball through the third conductive wire layer.

11. The semiconductor package of claim 1 , wherein the first conductive wire layer is a redistribution layer.

12. A semiconductor device, comprising:
a semiconductor package, comprising:
a first conductive wire layer with a first mounting area and a second mounting area, wherein the first mounting area and the second mounting area do not overlapped;
an integrated circuit (IC) disposed on a first surface of the first mounting area, wherein the IC is electrically insulated from the first conductive wire layer;
a radiation fin structure, disposed on a second surface of the first mounting area; and
an antenna, disposed on the second mounting area; and
a printed circuit board, connected to the semiconductor package by at least one solder ball.

13. The semiconductor device of claim 12 , wherein the antenna is disposed on a surface of the second mounting area, and the second surface of the first mounting area and the surface of the second mounting area are in the same plane.

14. The semiconductor device of claim 12 , wherein the antenna is disposed side-by-side to the heat dissipation structure.

15. The semiconductor device of claim 12 , further comprising:
a first thermal paste layer, disposed between the IC and the second surface of the first conductive wire layer to form a heat dissipation path from the IC to the radiation fin structure through the first conductive wire layer, wherein the first thermal paste layer is formed by thermally conductive and electrically insulated material.

16. The semiconductor device of claim 12 , wherein the antenna comprises at least one first antenna patch, and the at least one first antenna patch is formed in the first conductive wire layer.

17. The semiconductor device of claim 12 , further comprising:
a dielectric layer, formed on the second surface of the first conductive wire layer; and
at least one second antenna patch of the antenna, formed on the dielectric layer.

18. The semiconductor device of claim 17 , wherein the dielectric layer comprises an air cavity that is disposed side-by-side to the heat dissipation structure.

19. The semiconductor device of claim 12 , further comprising:
a second conductive wire layer, disposed between a substrate and the first conductive wire layer, wherein the second conductive wire layer contacts the first conductive wire layer, and the radiation fin structure is mounted to the second surface of the first conductive wire layer through the second conductive wire layer.

20. A method for packaging a semiconductor device, comprising:
providing a first conductive wire layer with a first mounting area and a second mounting area, wherein the first mounting area and the second mounting area do not overlapped;
disposing an integrated circuit (IC) on a first surface of the first mounting area, wherein the IC is electrically insulated from the first conductive wire layer;
disposing a radiation fin structure on a second surface of the first mounting area; and
providing an antenna on the second mounting area.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Albert
• Shih Chao-Wen
• Pu Han-Ping
• Pan Hsin-Yu
• Hsu Sen-Kuei

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title