Package-on-package structure

Patent metadata

Field	Value
Publication number	US-10867849-B2
Application number	US-201916714822-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Jun 29, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.

First claim

What is claimed is:

1. A package-on-package (PoP) structure, comprising:
a first package, comprising:
a die having an active surface and a rear surface opposite to the active surface, wherein the die comprises an amorphous layer located on the rear surface;
a plurality of conductive structures surrounding the die;
an encapsulant encapsulating the die and the plurality of conductive structures; and
a redistribution structure on the active surface of the die, wherein the redistribution structure is electrically connected to the plurality of conductive structures and the die; and

a second package stacked on the first package.

2. The PoP structure according to claim 1 , wherein the amorphous layer comprises an amorphous silicon layer.

3. The PoP structure according to claim 1 , wherein a ratio of a thickness of the amorphous layer to a thickness of the die ranges between about 1:133.3 and about 1:250000.

4. The PoP structure according to claim 1 , wherein a thickness of the amorphous layer ranges between about 1 nm and about 300 nm.

5. The PoP structure according to claim 1 , wherein a surface of the amorphous layer is substantially coplanar with a surface of the encapsulant.

6. The PoP structure according to claim 1 , wherein a surface of the amorphous layer is located at a different level height from a surface of the encapsulant.

7. The PoP structure according to claim 1 , further comprising a plurality of conductive terminals on the redistribution structure.

8. The PoP structure according to claim 1 , further comprising:
a plurality of joint terminals sandwiched between the first package and the second package; and
an underfill encapsulating the plurality of joint terminals.

9. The PoP structure according to claim 8 , wherein the underfill is in direct contact with the amorphous layer.

10. A package-on-package (PoP) structure, comprising:
a first package, comprising:
a die having an active surface and a rear surface opposite to the active surface, wherein the die comprises an amorphous layer located on the rear surface;
an encapsulant encapsulating the die, wherein a thickness of the die is smaller than a thickness of the encapsulant; and
a redistribution structure on the active surface of the die, wherein the redistribution structure is electrically connected to the die; and

a second package stacked on the first package.

11. The PoP structure according to claim 10 , wherein the amorphous layer comprises an amorphous silicon layer.

12. The PoP structure according to claim 10 , further comprising a plurality of conductive structures surrounding the die, wherein a thickness of the plurality of conductive structures is smaller than the thickness of the encapsulant.

13. The PoP structure according to claim 10 , further comprising:
a plurality of joint terminals sandwiched between the first package and the second package; and
an underfill encapsulating the plurality of joint terminals.

14. The PoP structure according to claim 13 , wherein the underfill is in direct contact with the amorphous layer and the encapsulant.

15. A package-on-package (PoP) structure, comprising:
a first package, comprising:
a die having an active surface and a rear surface opposite to the active surface, wherein the die comprises an amorphous layer located on the rear surface;
a plurality of conductive structures surrounding the die, wherein each of the plurality of conductive structures comprises a conductive pattern and a seed layer pattern disposed on the conductive pattern; and
an encapsulant encapsulating the die and the plurality of conductive structures, wherein top surfaces of the seed layer patterns are located at a level height lower than a top surface of the encapsulant; and

a second package stacked on the first package.

16. The PoP structure according to claim 15 , wherein sidewalls of each seed layer pattern are aligned with sidewalls of the corresponding conductive pattern.

17. The PoP structure according to claim 15 , wherein the amorphous layer comprises an amorphous silicon layer.

18. The PoP structure according to claim 15 , wherein a top surface of the amorphous layer is located at a different level height from the top surface of the encapsulant.

19. The PoP structure according to claim 15 , further comprising:
a plurality of joint terminals sandwiched between the first package and the second package, wherein the plurality of joint terminals is directly in contact with the top surfaces of the seed layer patterns; and
an underfill encapsulating the plurality of joint terminals.

20. The PoP structure according to claim 15 , further comprising:
a redistribution structure on the active surface of the die, wherein the redistribution structure is electrically connected to the plurality of conductive structures and the die; and
a plurality of conductive terminals on the redistribution structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Li-Hui
• Kao Chin-Fu
• Chien Chih-Yuan
• Lu Szu-Wei

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title