IR assisted fan-out wafer level packaging using silicon handler

Patent metadata

Field	Value
Publication number	US-10522406-B2
Application number	US-201815903973-A
Country	US
Kind code	B2
Filing date	Feb 23, 2018
Priority date	Mar 30, 2016
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface opposite the first surface, a release layer is located above the first surface of the silicon handler wafer, and a layer selected from the group consisting of an adhesive layer and a redistribution layer is located on a surface of the release layer. After building-up a fan-out wafer level package on the support structure, infrared radiation is employed to remove (via laser ablation) the release layer, and thus remove the silicon handler wafer from the fan-out wafer level package.

First claim

What is claimed is:

1. A support structure for use in fan-out wafer level packaging, the support structure comprising:
a silicon handler wafer having a first surface and a second surface opposite the first surface, wherein a first antireflective coating is present on the first surface of the silicon handler wafer, and a second antireflective coating is present on the second surface of the silicon handler wafer;
a release layer located above the first surface of the silicon handler wafer; and
an adhesive layer located on a surface of the release layer.

2. The support structure of claim 1 , further comprising a fan-out wafer level package present on a surface of the adhesive layer.

3. The support structure of claim 2 , wherein the fan-out wafer level package comprises a plurality of single semiconductor die.

4. The support structure of claim 2 , wherein the fan-out wafer level package comprises a plurality of semiconductor dies electrically connected to each other.

5. The support structure of claim 1 , wherein the adhesive layer is composed of silicon dioxide, a dielectric metal oxide or a dielectric metal oxynitride.

6. The support structure of claim 1 , wherein the release layer is composed of a metallic film or a layer of carbon.

7. The support structure of claim 1 , wherein the release layer is composed of a graphene layer or a layer of carbon nanotubes.

8. A support structure for use in fan-out wafer level packaging, the support structure comprising:
a silicon handler wafer having a first surface and a second surface opposite the first surface, wherein a first antireflective coating is present on the first surface of the silicon handler wafer, and a second antireflective coating is present on the second surface of the silicon handler wafer;
a release layer located above the first surface of the silicon handler wafer; and
a redistribution layer located on a surface of the release layer.

9. The support structure of claim 8 , where the redistribution layer is an element of a fan-out wafer level package.

10. The support structure of claim 9 , wherein the fan-out wafer level package further comprises a plurality of single semiconductor die or a plurality of semiconductor dies electrically connected to each other.

11. The support structure of claim 8 , wherein the release layer is composed of a metallic film or a layer of carbon.

12. The support structure of claim 8 , wherein the release layer is composed of a graphene layer or a layer of carbon nanotubes.

Assignees

• IBM
• Int Busniess Machines Corporation

Inventors

• Dang Bing
• Gelorme Jeffrey D
• Knickerbocker John U

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/014

  using batch processing · CPC title