Method and apparatus for implementing an application aware system on a programmable logic device

Patent metadata

Field	Value
Publication number	US-10867090-B2
Application number	US-201916356713-A
Country	US
Kind code	B2
Filing date	Mar 18, 2019
Priority date	Mar 18, 2019
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.

First claim

What is claimed is:

1. A method for designing a system on a target device, comprising:
synthesizing the system from a register transfer level description;
placing the system on the target device;
routing the system on the target device;
generating a configuration file that reflects the synthesizing, placing, and routing of the system for programming the target device;
identifying a modification for the system; and
modifying the configuration file to effectuate the modification for the system without changing the placing and routing of the system.

2. The method of claim 1 , wherein identifying the modification is performed in response to analyzing a register transfer level description of the system.

3. The method of claim 1 , wherein identifying the modification is performed in response to analyzing an input file provided by a user.

4. The method of claim 1 , wherein identifying the modification is performed by a state machine that analyzes an operating environment of the target device.

5. The method of claim 1 , wherein the synthesizing, placing, routing, and generating are performed by a first processing unit, and the identifying and modifying are performed by a second processing unit separate from the first processing unit.

6. The method of claim 5 , wherein the second processing unit is on the target device.

7. The method of claim 1 further comprising:
identifying another modification for the system;
modifying the modified configuration file to effectuate the another modification without changing the placing and routing of the system.

8. The method of claim 1 , wherein modifying the configuration file changes a look up table (LUT) mask that effectively reduces a number of select signals input into a multiplexer network.

9. The method of claim 8 , wherein the multiplexer network is implemented in a CLOS network.

10. The method of claim 1 , wherein modifying the configuration file changes a look up table (LUT) mask that effectively implements different multiplication values in a multiplier.

11. The method of claim 1 , wherein modifying the configuration file results in a reduction of a power requirement of the system.

12. The method of claim 1 , wherein modifying the configuration file changes coefficient values in a multiplier.

13. A method for designing a system on a target device, comprising:
placing the system on the target device;
routing the system on the target device;
compiling a description of the system to generate a configuration file that reflects the placing and routing of the system for programming the target device to implement the system;
identifying a modification for the system; and
modifying the configuration file to effectuate the modification for the system by changing a look up table (LUT) mask on the target device without changing the placing and routing of the system.

14. The method of claim 13 , wherein changing the LUT mask effectively reduces a number of select signals input into a multiplexer network.

15. The method of claim 13 , wherein changing the LUT mask effectively implements different multiplication values in a multiplier.

16. The method of claim 13 , wherein changing the LUT mask effectively implements different coefficients in an artificial neural network.

17. The method of claim 13 , wherein the compiling is performed by a first processing unit, and the identifying and modifying are performed on a second processing unit separate from the first processing unit.

18. The method of claim 17 , wherein the second system processing unit is on the target device.

19. The method of claim 13 further comprising:
identifying another modification for the system; and
modifying the modified configuration file to effectuate the another modification.

20. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device, comprising:
synthesizing the system from a register transfer level description;
placing the system on the target device;
routing the system on the target device;
generating a configuration file that reflects the synthesizing, placing, and routing of the system for programming the target device;
identifying a modification for the system; and
modifying the configuration file to effectuate the modification for the system without changing the placing and routing of the system.

21. The non-transitory computer readable medium of claim 20 , wherein identifying the modification is performed by a state machine that analyzes an operating environment of the target device.

22. The non-transitory computer readable medium of claim 20 , wherein the synthesizing, placing, routing, and generating are performed by a first processing unit, and the identifying and modifying are performed by a second processing unit separate from the first processing unit.

23. The non-transitory computer readable medium of claim 22 , wherein the second processing unit is on the target device.

24. The non-transitory computer readable medium of claim 20 , wherein modifying the configuration file changes a look up table (LUT) mask that effectively reduces a number of select signals input into a multiplexer network.

Assignees

• Intel Corp

Inventors

• Baeckler Gregg William
• Langhammer Martin
• Gribok Sergey
• Weber Scott J
• Steinke Gregory

Classifications

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F1/03

  working, at least partly, by table look-up (G06F1/025 takes precedence) · CPC title

• H03M7/6023

  Parallelization · CPC title

• H03M7/3082

  Vector coding (for television signals, see H04N19/94) · CPC title

• G06F30/347

  Physical level, e.g. placement or routing · CPC title