Sensor circuit, corresponding system and method

Patent metadata

Field	Value
Publication number	US-10866146-B2
Application number	US-201916356128-A
Country	US
Kind code	B2
Filing date	Mar 18, 2019
Priority date	Apr 13, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A circuit includes a first current source configured to produce a first current in a first current line through a first diode-connected transistor having a voltage drop across the first diode-connected transistor, the first current being proportional to an absolute temperature via a first proportionality factor; a second current source configured to produce a second current in a second current line through a second diode-connected transistor having a voltage drop across the second diode-connected transistor, the second current being proportional to the absolute temperature via a second proportionality factor; a third current source configured to produce a third current in a third current line through a third diode-connected transistor having a voltage drop across the third diode-connected transistor; and a processing network including a sigma-delta analog-to-digital converter, the processing network being coupled to the, the second, and the third diode-connected transistors.

First claim

What is claimed is:

1. A circuit, comprising:
a first current source configured to produce a first current in a first current line through a first diode-connected transistor having a voltage drop across the first diode-connected transistor, the first current being proportional to an absolute temperature via a first proportionality factor;
a second current source configured to produce a second current in a second current line through a second diode-connected transistor having a voltage drop across the second diode-connected transistor, the second current being proportional to the absolute temperature via a second proportionality factor, the second proportionality factor being different from the first proportionality factor;
a third current source configured to produce a third current in a third current line through a third diode-connected transistor having a voltage drop across the third diode-connected transistor; and
a processing network comprising a sigma-delta analog-to-digital converter, the processing network being coupled to the first diode-connected transistor, the second diode-connected transistor, and the third diode-connected transistor, wherein an output bitstream at an output node from the sigma-delta analog-to-digital converter has an average value providing a temperature sensing signal with a linear dependency on temperature, the processing network being sensitive to:
a difference of the voltage drops across the first diode-connected transistor and the second diode-connected transistor,
a difference of the voltage drops across the second diode-connected transistor and the third diode-connected transistor, and
the voltage drop across the second diode-connected transistor.

2. The circuit of claim 1 , wherein the sigma-delta analog-to-digital converter is active with opposed signs on:
the difference of the voltage drops across the first diode-connected transistor and the second diode-connected transistor; and
a combination of the difference of the voltage drops across the second diode-connected transistor and the third diode-connected transistor and the voltage drop across the second diode-connected transistor.

3. The circuit of claim 1 , wherein the third current is independent of temperature.

4. The circuit of claim 1 , further comprising a scaling circuit block coupled to the output node from the sigma-delta analog-to-digital converter and sensitive to the output bitstream from the sigma-delta analog-to-digital converter.

5. The circuit of claim 4 , wherein the scaling circuit block is configured to provide a scale conversion of the temperature sensing signal.

6. The circuit of claim 1 , wherein the processing network further comprises:
a first differential stage having inputs coupled to the first and the second diode-connected transistors, wherein the first differential stage is sensitive to a difference of the voltage drops across the first diode-connected transistor and the second diode-connected transistor, with an output signal from the first differential stage providing a first signal proportional to absolute temperature; and
a second differential stage having inputs coupled to the second and third diode-connected transistors, wherein the second differential stage is sensitive to a difference of the voltage drops across the second diode-connected transistor and the third diode-connected transistor, an output signal from the second differential stage providing a second signal proportional to absolute temperature.

7. The circuit of claim 6 , wherein the first differential stage has a first gain, denoted by symbol α, and the second differential stage has a second gain, denoted by symbol β, with an average value, denoted by symbol μ, of the output bitstream from the sigma-delta analog-to-digital converter given by a relationship,

µ
=

α
·
Δ

⁢

⁢

V
BE

V
BE

+

β
·
Δ

⁢

⁢

V

BE
,
comp

+

α
·
Δ

⁢

⁢

V
BE

where:
ΔV BE is the difference of the voltage drops across the first diode-connected transistor and the second diode-connected transistor;
ΔV BE,comp is the difference of the voltage drops across the second diode-connected transistor and the third diode-connected transistor; and
V BE is the voltage drop across the second diode-connected transistor, wherein the first gain and the second gain are set to values in which a denominator in the relationship is constant.

8. The circuit claim 7 , further comprising a combination network coupled to the first differential stage, the second differential stage, and a signal propagation path from the second diode-connected transistor, wherein the combination network is active on the output signal from the first differential stage, the output signal from the second differential stage, an input differential voltage, and the signal over the signal propagation path.

9. The circuit of claim 7 , further comprising a selection stage configured to render the sigma-delta analog-to-digital converter alternatively active on:
the difference of the voltage drops across the first diode-connected transistor and the second diode-connected transistor; and
the combination of the difference of the voltage drops across the second diode-connected transistor and the third diode-connected transistor and the voltage drop across the second diode-connected transistor.

10. The circuit of claim 9 , further comprising a feedback network from the output node of the sigma-delta analog-to-digital converter to the selection stage, wherein the selection stage is configured to operate as a function of a bitstream signal at the output node of the sigma-delta analog-to-digital converter.

11. The circuit of claim 10 , wherein the selection stage comprises:
a switching arrangement coupled to the first diode-connected transistor, the second diode-connected transistor, the third diode-connected transistor, the switching arrangement configured to sense the voltage drops across the first diode-connected transistor, the second diode-connected transistor, and the third diode-connected transistor, the switching arrangement coupled to the feedback network from the output node of the sigma-delta analog-to-digital converter; and
a capacitor bank between the switching arrangement and the sigma-delta analog-to-digital converter, the capacitor bank

Assignees

• St Microelectronics Srl

Inventors

• Ippolito Calogero Marco
• Vaiana Michele

Classifications

• G05F1/567

  for temperature compensation · CPC title

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/324

  characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement · CPC title

• G05F3/265

  using bipolar transistors only · CPC title