Network forwarding element with key-value processing in the data plane

Patent metadata

Field	Value
Publication number	US-10862827-B1
Application number	US-201916372370-A
Country	US
Kind code	B1
Filing date	Apr 1, 2019
Priority date	Oct 12, 2016
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

Some embodiments of the invention provide a forwarding element that has one or more data plane, message-processing pipelines with key-value processing circuits. The forwarding element's data plane key-value circuits allow the forwarding element to perform key-value services that would otherwise have to be performed by data compute nodes connected by the network fabric that includes the forwarding element. In some embodiments, the key-value (KV) services of the forwarding element and other similar forwarding elements supplement the key-value services of a distributed set of key-value servers by caching a subset of the most commonly used key-value pairs in the forwarding elements that connect the set of key-value servers with their client applications. In some embodiments, the key-value circuits of the forwarding element perform the key-value service operations at message-processing line rates at which the forwarding element forwards messages to the data compute nodes and/or to other network forwarding elements.

First claim

The invention claimed is:

1. A data-plane forwarding circuitry configured to forward data messages received by a forwarding element to other network elements in a network, the data-plane forwarding circuitry comprising:
a parser to access a message header from a received data message, the message header comprising a key-value instruction and a key;
a message processing pipeline configured to process the key-value instruction;
a memory to store a plurality of key values associated with a plurality of keys; and
a deparser, wherein:
when the key-value instruction is a read instruction:
the message processing pipeline is to access a key value from the memory and modify the accessed message header to include the accessed key value,
the data message is a first data message, and
the deparser is to combine the modified data message header with a payload to form a second data message to forward to a network element.

2. The data-plane forwarding circuitry of claim 1 , wherein the forwarding element is part of a plurality of forwarding elements that form a network fabric that communicatively connects key-value client machines with key-value server machines that execute a distributed key-value service application.

3. The data-plane forwarding circuitry of claim 1 , wherein the accessed data message header comprises a layer 4 port value that specifies that the data message contains a key-value instruction.

4. The data-plane forwarding circuitry of claim 1 , wherein the accessed data message header comprises a layer 4 option field that comprises the key-value instruction and the key.

5. The data-plane forwarding circuitry of claim 1 , wherein the key-value instruction comprises a read instruction, a write instruction, a delete instruction or an insert instruction.

6. The data-plane forwarding circuitry of claim 1 , wherein the memory is a first memory, the data-plane forwarding circuitry further comprising a match second memory to store a plurality of key records, at least one key record to store (i) a key, and (ii) a location in the first memory that stores a value associated with the key.

7. The data-plane forwarding circuitry of claim 6 , wherein the match second memory is to (i) determine whether the key in the accessed data message header matches a stored key in one of the key records stored in the match second memory, and when the stored key matches the key in the accessed data message header, (ii) output the location in the first memory for the key value corresponding to matched, stored key.

8. The data-plane forwarding circuitry of claim 7 , wherein when the key-value instruction is a write instruction, the first memory is to store, at the memory location output by the match second memory, a key value from the data message header.

9. The data-plane forwarding circuitry of claim 1 , wherein message processing pipeline comprises a plurality of data-plane stateful processing units (DSPUs), at least two DSPUs to read or write different portions of a key value to two different memories when the key value has a size that is too large to store in a record location in one memory.

10. The data-plane forwarding circuitry of claim 9 , wherein:
the message processing pipeline comprises a plurality of message processing stages to process header values associated with data messages to forward the data messages to other forwarding elements or to one or more data message destinations, and
two different DSPUs are in two different message processing stages.

11. The data-plane forwarding circuitry of claim 1 , wherein when the key-value instruction is a write instruction, the data message header includes a key value, and the key value from the data message header is provided to the message processing pipeline to direct the message processing pipeline to write the key value in the memory.

12. The data-plane forwarding circuitry of claim 1 , wherein the network element that is to receive the second data message comprises a key-value client machine that sent the first data message.

13. The data-plane forwarding circuitry of claim 1 , wherein the network element that is to receive the second data message is different than a key-value client machine that sent the first data message.

14. The data-plane forwarding circuitry of claim 7 , wherein the read instruction is accessed from the data message header and provided to the first memory along with the location output from the match second memory.

15. The data-plane forwarding circuitry of claim 7 , wherein the first memory is to (i) receive the location provided by the match second memory and (ii) read the key value from the location, write a key value to the location, or invalidate the key value stored at the location.

16. The data-plane forwarding circuitry of claim 1 , wherein the network elements comprise forwarding elements and machines that send and receive messages through the forwarding elements.

17. The data-plane forwarding circuitry of claim 1 , wherein:
the message processing pipeline comprises a plurality of message processing stages to process header values associated with data messages to forward the data messages to other forwarding elements or to one or more data message destinations; and
at least one of the message processing stages comprises a data-plane stateful processing unit (DSPU).

Assignees

• Barefoot Networks Inc

Inventors

• Li Xiaozhou
• Lee Jeongkeun
• Kim Changhoon
• Foster John Nathan

Classifications

• G06F3/061 Primary

  Improving I/O performance · CPC title

• H04L49/3009 Primary

  Header conversion, routing tables or routing tags · CPC title

• G06F3/0649

  Lifecycle management · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• H04L45/745

  Address table lookup; Address filtering · CPC title