Memory arrangement for implementation of high-throughput key-value stores

Patent metadata

Field	Value
Publication number	US-9323457-B2
Application number	US-201314100250-A
Country	US
Kind code	B2
Filing date	Dec 9, 2013
Priority date	Dec 9, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.

First claim

What is claimed is:

1. A circuit for processing data, the circuit comprising:
an input for receiving a request for implementing a key-value store data transaction that enables access to a store associated with a key;
a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store;
a first memory device of a first type storing a first portion of a value of a store associated with the key-value store data transaction;
a second memory device of a second type storing a second portion of the value of the store associated with the key-value store data transaction, wherein the second portion of the value of the store associated with the key-value store data transaction is different than the first portion of the value of the store associated with the key-value store data transaction; and
a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion.

2. The circuit of claim 1 wherein the memory management circuit controls the routing of a data block into a first data portion and a second data portion.

3. The circuit of claim 2 wherein the memory management circuit enables routing the first data portion of the data block by way of a first memory interface and routing the second data portion of the data block by way of a second memory interface.

4. The device of claim 1 wherein the memory management circuit routes a block of data to a selected memory type based upon an access criterion.

5. The circuit of claim 4 wherein the access criterion is based upon a size of the data of the data block.

6. The circuit of claim 4 wherein the access criterion is based upon an access frequency of the data of the data block.

7. The circuit of claim 1 wherein the plurality of memory interfaces comprises a first memory interface which enables routing data to a DRAM and a second memory interface which enables routing data to an SSD memory.

8. A circuit for processing data, the circuit comprising:
an input for receiving a request for implementing a key-value store data transaction that enables access to a store associated with a key;
a first memory interface enabling access to a memory location of a first type of memory storing a first portion of a value of a store associated with a key-value store;
a second memory interface enabling access to a memory location of a second type of memory storing a second portion of the value of the store associated with the key-value store, wherein the second portion of the value of the store associated with the key-value store is different than the first portion of the value of the store associated with the key-value store; and
a memory management circuit coupled between the input and the first and second memory interfaces, the memory management circuit controlling the routing of data by way of the first and second memory interfaces based upon a data transfer criterion.

9. The circuit of claim 8 wherein the memory management circuit routes a first portion of a data block by way of the first memory interface and a second portion of the data block by way of the second memory interface.

10. The circuit of claim 8 wherein the memory management circuit routes data by way of either the first memory interface or the second memory interface based upon a size of the data.

11. The circuit of claim 8 wherein the memory management circuit routes data by way of either the first memory interface or the second memory interface based upon an access frequency of the data.

12. The circuit of claim 8 wherein the first memory interface enables routing data to a DRAM memory and the second memory interface enables routing data to an SSD memory.

13. The circuit of claim 12 wherein data routed by way of the second memory interface is stored in multiple memory devices.

14. The device of claim 13 wherein the memory management circuit enables simultaneously accessing different blocks of data in the multiple memory devices.

15. A method of processing data, the method comprising:
receiving a request for implementing a data transaction associated with a key-value store that enables access to a store associated with a key;
controlling the routing of data by way of a plurality of memory interfaces based upon a data transfer criterion, wherein a first memory device of a first type of memory stores a first portion of a value of a store associated with the data transaction and a second memory device of a second type of memory stores a second portion of the value of the store associated with the data transaction that is different than the first portion of the value of the store associated with the data transaction;
enabling accessing a memory location of the first memory device associated with the key-value store by way of a first memory interface; and
enabling accessing a memory location of the second memory device associated with the key-value store by way of a second memory interface.

16. The method of claim 15 wherein controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion comprises routing a first portion of a data block by way of the first memory interface and a second portion of the data block by way of the second memory interface.

17. The method of claim 15 wherein controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion comprises routing data by way of either the first memory interface or the second memory interface based upon a size of the data.

18. The method of claim 15 wherein controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion comprises routing data by way of either the first memory interface or the second memory interface based upon an access frequency of the data.

19. The method of claim 15 wherein enabling accessing a memory location of the first memory device associated with the key-value store by way of a first memory interface comprises routing data to an SSD memory.

20. The method of claim 19 wherein enabling accessing a memory location of the second memory device associated with the key-value store by way of a second memory interface comprises routing data to a DRAM.

Assignees

• Xilinx Inc

Inventors

• Blott Michaela
• Liu Ling
• Vissers Kornelis A

Classifications

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F16/22 Primary

  Indexing; Data structures therefor; Storage structures · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F16/24569

  Query processing with adaptation to specific hardware, e.g. adapted for using GPUs or SSDs · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title