Memory device with reduced capacitance

Patent metadata

Field	Value
Publication number	US-10861867-B2
Application number	US-201816021550-A
Country	US
Kind code	B2
Filing date	Jun 28, 2018
Priority date	Jun 28, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory array formed in a die, wherein the memory array includes one or more pillars and a plurality of wordlines coupled with the one or more pillars,
wherein adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, wherein the dielectric layers include composites of dielectric materials, wherein a composite includes a first dielectric material with a first dielectric constant and a second dielectric material with a second dielectric constant, wherein the first and second dielectric constants comprise low-k dielectric constants, wherein the composite is free from an air gap, wherein the first dielectric constant is lower than the second dielectric constant, wherein the first dielectric material is disposed completely inside the second dielectric material, wherein the composite is provided to reduce capacitance of the plurality of wordlines.

2. The apparatus of claim 1 , wherein each of the one or more pillars comprise one or more memory cells formed in a stacked fashion.

3. The apparatus of claim 1 , wherein a wordline of the plurality of wordlines includes a gate to control a memory cell coupled with the wordline, wherein the gate comprises one of: a metal or a silicon-based material.

4. The apparatus of claim 3 , wherein the metal comprises tungsten (W).

5. The apparatus of claim 3 , wherein the silicon-based material comprises polysilicon.

6. The apparatus of claim 1 , wherein the memory array comprises a three-dimensional (3D) NAND memory array.

7. The apparatus of claim 1 , wherein the apparatus comprises an integrated circuit.

8. A computing system, comprising:
a processor; and
a memory coupled with the processor, wherein the memory includes a memory array formed in a die, wherein the memory array includes one or more pillars and a plurality of wordlines coupled with the one or more pillars, wherein adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, wherein the dielectric layers include composites of dielectric materials, wherein a composite includes a first dielectric material with a first dielectric constant and a second dielectric material with a second dielectric constant, wherein the first and second dielectric constants comprise low-k dielectric constants, wherein the composite is free from an air gap, wherein the first dielectric constant is lower than the second dielectric constant, wherein the first dielectric material is disposed completely inside the second dielectric material, wherein the composite is provided to reduce capacitance of the plurality of wordlines.

9. The computing system of claim 8 , wherein each of the one or more pillars comprise one or more memory cells formed in a stacked fashion.

10. The computing system of claim 8 , wherein a wordline of the plurality of wordlines includes a gate to control a memory cell coupled with the wordline, wherein the gate comprises one of: a metal or a silicon-based material.

11. The computing system of claim 8 , wherein the computing system is a mobile computing device.

12. A method, comprising:
forming one or more pillars comprising memory cells in a die, to form a memory array; and
providing a plurality of wordlines to couple with respective ones of the one or more pillars, including separating adjacent wordlines of the plurality of wordlines by respective dielectric layers, wherein the dielectric layers include composites of dielectric materials, wherein a composite includes a first dielectric material with a first dielectric constant and a second dielectric material with a second dielectric constant, wherein the first and second dielectric constants comprise low-k dielectric constants, wherein the composite is free from an air gap, wherein the first dielectric constant is lower than the second dielectric constant, wherein the first dielectric material is disposed completely inside the second dielectric material, wherein the composite is provided to reduce capacitance of the plurality of wordlines.

13. The method of claim 12 , wherein providing the plurality of wordlines includes, for a wordline, forming a gate to control a memory cell coupled with the wordline, wherein the gate comprises one of: a metal or a silicon-based material.

14. The method of claim 12 , wherein the memory array comprises a three dimensional (3D) NAND memory array.

Assignees

• Intel Corp

Inventors

• Hasnat Khaled
• Majhi Prashant
• Parat Krishna

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title