Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9666525-B2
Application number	US-201615201994-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Aug 28, 2015
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.

First claim

What is claimed is:

1. A three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, comprising:
a substrate;
a stack structure on the substrate, the stack structure including a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes alternately stacked on each other, at least one of the ILD layers including pores;
a vertical structure penetrating the stack structure and electrically connected to the substrate; and
a data storage layer between the stack structure and the vertical structure.

2. The 3D memory device of claim 1 , wherein the pores have different densities with respect to regions in the at least one of the ILD layers.

3. The 3D memory device of claim 1 , wherein the at least one of the ILD layers includes a material having a dielectric constant smaller than silicon oxide.

4. The 3D memory device of claim 1 , wherein the at least one of the ILD layers includes a first sub-ILD layer and a second sub-ILD layer, and the first and second sub-ILD layers are different from each other in terms of at least one of dielectric constants, thicknesses, porosities, and pore sizes.

5. The 3D memory device of claim 1 , wherein the at least one of the ILD layers includes a first sub-ILD layer and a second sub-ILD layer, the first sub-ILD layer has a dielectric constant comparable to silicon oxide, and the second sub-ILD layer includes the pores and has a dielectric constant smaller than the first sub-ILD layer.

6. The 3D memory device of claim 1 , wherein a first ILD layer from among the ILD layers, one gate electrode from among the gate electrodes on the first ILD layer, and a second ILD layer from among the ILD layers on the one gate electrode have a thickness relationship such that thicknesses of the first ILD layer, the gate electrode, and the second ILD layer increase in an order named.

7. The 3D memory device of claim 1 , wherein at least two of the ILD layers have substantially different thicknesses from each other.

8. The 3D memory device of claim 1 , wherein side surfaces of the ILD layers protrude past side surfaces of the gate electrodes.

9. The 3D memory device of claim 1 , wherein the at least one of the ILD layers including pores includes at least one of:
a top ILD layer including the pores and being located at a top of the stack structure;
a center ILD layer including the pores and being at a center of the stacked structure;
a bottom ILD layer including the pores and being located at a bottom of the stack structure.

10. The 3D memory device of claim 1 , wherein the at least one of the ILD layers including the pores is provided in plurality in a sparse manner.

11. The 3D memory device of claim 1 , wherein
the vertical structure includes a first portion and a second portion,
the first portion has a pipe shape and is closed at a bottom thereof,
the second portion has a pipe shape and is connected to the first portion, and
the first portion electrically connects the second portion to the substrate.

12. The 3D memory device of claim 11 , wherein the closed bottom of the first portion is lower than a top surface of the substrate.

13. The 3D memory device of claim 1 , wherein the data storage layer includes a first portion extending between the vertical structure and the stack structure and a second portion horizontally extending between the ILD layers and the gate electrodes.

14. The 3D memory device of claim 1 , wherein a dielectric constant of the at least one of the ILD layers is lower than a dielectric constant of the data storage layer.

15. A three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, comprising:
peripheral circuitry; and
a cell array structure on the peripheral circuitry and electrically connected to the peripheral circuitry, the cell array structure including,
a substrate;
a stack structure including a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes alternately stacked, at least one of the ILD layers including pores;
a vertical structure penetrating the stack structure and electrically connected to the substrate; and
a data storage layer between the stack structure and the vertical structure.

16. The 3D memory device of claim 15 , wherein the pores are distributed in different densities according to regions in the at least one of the ILD layers.

17. The 3D memory device of claim 15 , wherein the at least one of the ILD layers includes a material having a dielectric constant smaller than silicon oxide.

18. The 3D memory device of claim 15 , wherein when the at least one of the ILD layers includes a first sub-ILD layer and a second sub-ILD layer, and the first and second sub-ILD layers are different from each other in terms of at least one of dielectric constants, thicknesses, porosities, and pore sizes.

19. The 3D memory device of claim 15 , wherein the at least one of the ILD layers includes a first sub-ILD layer and a second sub-ILD layer, the first sub-ILD layer has a dielectric constant comparable to silicon oxide, and the second sub-ILD layer includes the pores and has a dielectric constant smaller than silicon oxide.

20. A three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, comprising:
a substrate;
a stack structure on the substrate, the substrate including a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes alternately stacked on each other, the ILD layers including at least one non-porous ILD layer having a first dielectric constant and at least one porous ILD layer having a second dielectric constant, the second dielectric constant being smaller than the first dielectric constant;
a vertical structure penetrating the stack structure and electrically connected to the substrate; and
a data storage layer between the stack structure and the vertical structure.

Assignees

• Kim Jeeyong
• Byeon Daeseok
• Lee Jung-Hwan
• Ahn Sanghoon
• Samsung Electronics Co Ltd

Inventors

• Kim Jeeyong
• Byeon Daeseok
• Lee Jung-Hwan
• Ahn Sanghoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L23/5226 Primary

  Electricity · mapped topic