Method for performing data management in memory device, associated memory device and controller thereof

Patent metadata

Field	Value
Publication number	US-10860422-B2
Application number	US-201916431679-A
Country	US
Kind code	B2
Filing date	Jun 4, 2019
Priority date	Jan 3, 2017
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.

First claim

What is claimed is:

1. A controller of a memory device, the memory device comprising the controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory chip, the controller comprising:
a processing circuit, arranged to control the controller to receive a set of data from a host device positioned outside the memory device; and
a data protection circuit, coupled to the processing circuit, the data protection circuit arranged to perform error correction, wherein:
the data protection circuit encodes the set of data according to a first sub-matrix of a predetermined parity-check matrix, to generate a partial parity-check code; and
the data protection circuit performs post-processing upon the partial parity-check code according to a predetermined post-processing matrix, to generate a parity-check code of the set of data, wherein the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix;

wherein the processing circuit controls the controller to write a codeword of the set of data into the non-volatile memory, to allow the memory device to perform error correction when reading the set of data from the non-volatile memory, wherein the codeword comprises the set of data and the parity-check code.

2. The controller of claim 1 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined parity-check matrix is not the predetermined coding transformation matrix.

3. The controller of claim 1 , wherein the codeword is equal to a multiplication result of the set of data and a predetermined coding transformation matrix; and the predetermined post-processing matrix is not the predetermined coding transformation matrix.

Assignees

• Silicon Motion Inc

Inventors

• Wang Yu-Luen

Classifications

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/611

  Specific encoding aspects, e.g. encoding by means of decoding · CPC title

• H03M13/1148

  Structural properties of the code parity-check or generator matrix · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title