Method to distribute user data and error correction data over different page types by leveraging error rate variations

Patent metadata

Field	Value
Publication number	US-9262268-B2
Application number	US-201414173108-A
Country	US
Kind code	B2
Filing date	Feb 5, 2014
Priority date	Dec 20, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.

First claim

The invention claimed is:

1. An apparatus comprising:
a memory comprising a plurality of memory devices, each memory device having a plurality of pages, wherein the plurality of pages in each memory device are classified into a plurality of different types of pages based on error rate variations among the pages in each memory device; and
a controller configured to write user data and error-correction data to a super-page of the memory, wherein the super-page comprises a plurality of sub-pages including user data pages and one or more parity data pages, the plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using two or more types of pages, and calculation of the one or more parity data pages by the controller is divided into a number of portions corresponding to a number of types of pages used to store the sub-pages of the super-page.

2. The apparatus according to claim 1 , wherein the plurality of types of pages comprise one or more of upper and lower pages, odd and even pages, and least significant bit and most significant bit pages.

3. The apparatus according to claim 1 , wherein adjacent sub-pages of the super-page are stored in different types of pages.

4. The apparatus according to claim 1 , wherein the plurality of types of pages are based one or more of physical location within each of the memory devices and logical location in a memory cell.

5. The apparatus according to claim 1 , wherein the controller stores the user data pages of the super-page across the plurality of memory devices using a barber pole pattern.

6. The apparatus according to claim 1 , wherein the plurality of memory devices comprise one or more flash memory dies.

7. The apparatus according to claim 1 , wherein the memory and the controller are part of a solid state drive or disk.

8. The apparatus according to claim 1 , wherein the controller writes a row of user data to memory immediately and writes parity data for a plurality of rows of user data simultaneously.

9. A method of distributing data over a plurality of memory devices comprising the steps of:
classifying each of a plurality of pages in each of a plurality of memory devices into a plurality of types of pages, wherein the plurality of types of pages are based on error rate variations among the pages of each memory device;
writing user data and error-correction data to a super-page, wherein the super-page comprises a plurality of sub-pages including user data pages and one or more parity data pages, and the plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using two or more types of pages; and
calculating the one or more parity data pages in a number of individual portions corresponding to a number of types of pages used to store the sub pages of the super-page.

10. The method according to claim 9 , wherein the plurality of types of pages comprise one or more of upper and lower pages, odd and even pages, and least significant bit and most significant bit pages.

11. The method according to claim 9 , wherein adjacent sub-pages of the super-page are stored in different types of pages.

12. The method according to claim 9 , wherein the plurality of types of pages are based one or more of physical location within each of the memory devices and logical location in a memory cell.

13. The method according to claim 9 , wherein the user data is stored across the plurality of memory devices using a barber pole pattern.

14. The method according to claim 9 , further comprising writing a row of user data to memory immediately and writing parity data for a plurality of rows of user data simultaneously.

15. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory comprising a plurality of memory devices with each memory device comprising a plurality of pages, wherein the plurality of pages in each memory device are classified into a plurality of different types based on error rate variations; and
a control circuit configured to write user data and error-correction data to a super-page of the memory, wherein the super-page comprises a plurality of sub-pages including user data pages and one or more parity data pages, the plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using two or more types of pages, and calculation of the one or more parity data pages by the control circuit is divided into a number of portions corresponding to a number of types of pages used to store the sub-pages of the super-page.

16. The apparatus according to claim 15 , wherein the plurality of types of pages comprise one or more of upper and lower pages, odd and even pages, and least significant bit and most significant bit pages.

17. The apparatus according to claim 15 , wherein adjacent sub-pages of the super-page are stored in different types of pages.

18. The apparatus according to claim 15 , wherein the plurality of types of pages are based one or more of physical location within each of the memory devices and logical location in a memory cell.

19. The apparatus according to claim 15 , wherein the super-page contains data from a number of user data rows corresponding to the number of types of pages used to store the super-page.

20. The apparatus according to claim 15 , wherein each portion of parity data calculated is stored in a different memory device.

Assignees

• Seagate Technology Llc

Inventors

• Cai Yu
• Chen Ning
• Wu Yunxiang
• Haratsch Erich F
• Cohen Earl T
• Canepa Timothy L

Classifications

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title