Silicon carbide epitaxial substrate and silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-10858757-B2
Application number	US-201716097966-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	May 20, 2016
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.

First claim

The invention claimed is:

1. A silicon carbide epitaxial substrate comprising:
a silicon carbide single-crystal substrate;
a first epitaxial layer disposed on the silicon carbide single-crystal substrate;
a second epitaxial layer disposed on the first epitaxial layer; and
a third epitaxial layer disposed on the second epitaxial layer,
wherein when the number of basal plane dislocations included in a lower surface of the first epitaxial layer is a, an upper surface of the second epitaxial layer includes a×0.001 or less number of basal plane dislocations, and
the first epitaxial layer has a basal-plane-dislocation conversion rate lower than a basal-plane-dislocation conversion rate in the second epitaxial layer.

2. The silicon carbide epitaxial substrate according to claim 1 , wherein
the first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%, and
the second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.

3. The silicon carbide epitaxial substrate according to claim 1 , wherein the first epitaxial layer and the second epitaxial layer have an impurity concentration of 1×10 16 cm −3 or more and 1×10 19 cm −3 or less.

4. The silicon carbide epitaxial substrate according to claim 1 , wherein 0.01≤Nb/Na≤1 is satisfied, wherein Na is an impurity concentration of the first epitaxial layer, wherein Nb is an impurity concentration of the second epitaxial layer.

5. A silicon carbide semiconductor device comprising the silicon carbide epitaxial substrate according to claim 1 .

6. The silicon carbide semiconductor device according to claim 5 , wherein
the first epitaxial layer and the second epitaxial layer constitute a buffer layer, and
the third epitaxial layer constitutes a drift layer.

7. A silicon carbide epitaxial substrate comprising:
a silicon carbide single-crystal substrate;
a first epitaxial layer disposed on the silicon carbide single-crystal substrate;
a second epitaxial layer disposed on the first epitaxial layer; and
a third epitaxial layer disposed on the second epitaxial layer,
wherein when the number of basal plane dislocations included in a lower surface of the first epitaxial layer is a, an upper surface of the second epitaxial layer includes a×0.001 or less number of basal plane dislocations, wherein
a basal plane dislocation and a step flow direction forms an angle of ±45° or less, the basal plane dislocation being included in an interface between the first epitaxial layer and the second epitaxial layer, and in the second epitaxial layer.

8. A silicon carbide semiconductor device comprising:
a silicon carbide epitaxial substrate, the silicon carbide epitaxial substrate including
a silicon carbide single-crystal substrate;
a first epitaxial layer disposed on the silicon carbide single-crystal substrate;
a second epitaxial layer disposed on the first epitaxial layer;
a third epitaxial layer disposed on the second epitaxial layer; and
a fourth epitaxial layer disposed on the third epitaxial layer and having a lower impurity concentration than the third epitaxial layer,

when the number of basal plane dislocations included in a lower surface of the first epitaxial layer is a, an upper surface of the second epitaxial layer includes a×0.001 or less number of basal plane dislocations,
the first epitaxial layer, the second epitaxial layer, and the third second epitaxial layer constitute a buffer layer, and
the fourth epitaxial layer constitutes a drift layer.

Assignees

• Mitsubishi Electric Corp

Inventors

• Tanaka Takanori
• Yamamoto Shigehisa
• Nakamura Yu
• Kimura Yasuhiro
• Nakata Shuhei
• Mitani Yoichiro

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3208

  Silicon carbide · CPC title