Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device

Patent metadata

Field	Value
Publication number	US-10855495-B2
Application number	US-201916574814-A
Country	US
Kind code	B2
Filing date	Sep 18, 2019
Priority date	Jun 22, 2017
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.

First claim

What is claimed is:

1. An apparatus comprising:
a driver circuit coupled to a terminal of a chip; and
an arbiter circuit configured to enable the driver circuit to change a voltage of the terminal before determining a resistor coupled to the terminal is available for a calibration operation of the chip, wherein the arbiter circuit enables the driver circuit based at least in part, on timing information unique to the chip.

2. The apparatus of claim 1 , further comprising a calibration control circuit coupled to the driver circuit, wherein the calibration control circuit is configured to adjust an impedance of the driver circuit when the resistor is available for the calibration operation.

3. The apparatus of claim 1 , wherein the driver circuit includes a pull-up circuit and a pull-down circuit.

4. The apparatus of claim 3 , wherein the pull-up circuit includes a first plurality of transistors coupled in parallel between a first power supply terminal and a node and the pull-down circuit includes a second plurality of transistors coupled in parallel between a second power supply terminal and the node.

5. The apparatus of claim 1 , further comprising a comparator configured to compare a first voltage to a reference voltage and provide a comparator result to the arbiter circuit.

6. The apparatus of claim 5 , further comprising a reference voltage generator configured to provide the reference voltage to the comparator.

7. The apparatus of claim 5 , further comprising a multiplexer, wherein the multiplexer is configured to provide either the voltage of the terminal or an intermediate voltage as the first voltage to the comparator.

8. The apparatus of claim 7 , wherein the driver circuit includes a pull-up circuit and a pull-down circuit and the intermediate voltage is a voltage at a node between the pull-up circuit and the pull-down circuit.

9. The apparatus of claim 1 , wherein arbiter circuit includes a register and the timing information unique to the chip is stored in the register.

10. An apparatus comprising:
a first driver circuit coupled to a terminal of a chip;
a second driver circuit; and
an arbiter circuit coupled to the first driver circuit and the second driver circuit, wherein the arbiter circuit is configured to enable the first driver circuit and the second driver circuit by providing a first code, wherein when the arbiter circuit provides the first code is based at least in part, on timing information unique to the chip.

11. The apparatus of claim 10 , further comprising:
a third driver circuit coupled to the second driver circuit at the node; and
a calibration code control circuit configured to receive the first code and provide a second code to enable the third driver circuit, wherein the second code is based, at least in part, on the timing information unique to the chip.

12. The apparatus of claim 11 , wherein the first driver circuit includes a first pull-down circuit, the second driver circuit includes a second pull-down circuit, and the third driver circuit includes a pull-up circuit.

13. The apparatus of claim 10 , further comprising a comparator configured to compare a first voltage to a reference voltage and provide a comparator result to the arbiter circuit.

14. The apparatus of claim 13 , further comprising:
a third driver circuit coupled to the second driver circuit at the node; and
a multiplexer configured to provide the first voltage to the comparator, wherein the multiplexer is configured to provide either a voltage of the terminal or a voltage of the node as the first voltage.

15. The apparatus of claim 14 , wherein whether the multiplexer provides the voltage of the terminal or the voltage of the node, is based, at least in part, on whether an arbitration operation or a calibration operation is being performed.

16. The apparatus of 13 , further comprising a calibration code control circuit configured to receive the first code from the arbiter circuit and the comparator result from the comparator circuit, wherein the calibration code control circuit is further configured to provide a second code to enable the third driver circuit, wherein the second code is based, at least in part, on the timing information unique to the chip.

17. An apparatus comprising:
a driver circuit coupled to a terminal of a chip;
an arbiter circuit; and
a calibration control circuit coupled to the driver circuit, the calibration control circuit configured to adjust an impedance of the driver circuit after determining a resistor coupled to the terminal is available for a calibration operation of the chip, wherein determining the resistor coupled to the terminal is available is based at least in part, on timing information unique to the chip.

18. The apparatus of claim 17 , wherein the arbiter circuit is configured to disable the driver circuit to change a voltage of the terminal for a predetermined time at a beginning of a fixed duration of time, based at least in part, on the timing information unique to the chip.

19. The apparatus of claim 18 , wherein the arbiter circuit is further configured to enable the driver circuit after the predetermined time.

20. The apparatus of claim 17 , wherein the arbiter circuit is configured to enable and disable the driver circuit for a fixed duration of time, based at least in part, on the timing information unique to each chip.

Assignees

• Micron Technology Inc

Inventors

• Wieduwilt Christopher G
• Johnson Jason

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C29/025 Primary

  in signal lines · CPC title