Device having multiple channels with calibration circuit shared by multiple channels

Patent metadata

Field	Value
Publication number	US-9666245-B2
Application number	US-201514695837-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	May 21, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

First claim

What is claimed is:

1. An apparatus comprising:
a first channel including a first command control circuit, a first memory cell array configured to be controlled by the first command control circuit and a first data output circuit configured to output first data from the first memory cell array with first impedance controlled responsive to a first calibration code;
a second channel provided independently of the first channel, the second channel including a second command control circuit, a second memory cell array configured to be controlled by the second command control circuit and a second data output circuit configured to output second data from the second memory cell array with second impedance controlled responsive to a second calibration code; and
a calibration circuit provided in common to the first channel and the second channel to provide the first calibration code responsive to a first calibration control signal from the first command control circuit and a second calibration code responsive to a second calibration control signal from the second command control circuit.

2. The apparatus of claim 1 , wherein the first channel includes a first data terminal coupled to the first data output circuit and a second data terminal coupled to the second data output circuit.

3. The apparatus of claim 2 , wherein the first channel includes a first command terminal coupled to the first command control circuit and the second channel includes a second command terminal coupled to the second command control circuit.

4. The apparatus of claim 3 , wherein the first command control circuit is configured to provide the first calibration control signal to the calibration circuit responsive to receiving a first calibration command through the first command terminal and the second command control circuit is configured to provide the second calibration control signal to the calibration circuit responsive to receiving a second calibration command through the second command terminal.

5. The apparatus of claim 4 , wherein the calibration circuit includes a code generator and an arbiter coupled to the code generator, the arbiter being configured to cancel the second calibration control signal on condition that the arbiter receives the second calibration control signal when the calibration circuit is in a calibration operation responsive to the first calibration control signal.

6. The apparatus of claim 5 , wherein the arbiter is configured to cancel the first calibration control signal on condition that the arbiter receives the first calibration control signal when the calibration circuit is in a calibration operation responsive to the second calibration control signal.

7. The apparatus of claim 6 , wherein the arbiter is configured to provide the first calibration code responsive to the first calibration control signal when the arbiter receives the first calibration control signal and the second calibration control signal at a substantially same time.

8. The apparatus of claim 1 , wherein the first channel includes a first relay circuit coupled between the first data output circuit and the calibration circuit and the second channel includes a second relay circuit coupled between the second data output circuit and the calibration circuit.

9. The apparatus of claim 8 , wherein the first relay circuit is configured to store the first calibration code responsive to a first update control signal provided from the first command control circuit and the second relay circuit is configured to store the second calibration code responsive to a second update control signal provided from the second command control circuit.

10. An apparatus comprising:
a controller including a first core comprising a first command terminal and a first data terminal and a second core comprising a second command terminal and a second data terminal, the first core and the second core being configured to issue a first calibration command to the first command terminal and a second calibration command to the second command terminal independently of each other; and
a first memory device including a first channel comprising a third command terminal coupled to the first command terminal, a third data terminal coupled to the first data terminal and a first data output circuit coupled to the third data terminal, a second channel comprising a fourth command terminal coupled to the second command terminal, a fourth data terminal coupled to the second data terminal and a second data output circuit coupled to the fourth data terminal, and a calibration circuit configured to provide a calibration code responsive to each of the first calibration command and the second calibration command.

11. The apparatus of claim 10 , further comprising a reference resistor, wherein the first memory device includes a calibration terminal coupled between the reference resistor and the calibration circuit.

12. The apparatus of claim 10 , wherein the first core is configured to issue a first update command at the first command terminal and the second core is configured to issue a second update command at the second command terminal independently, impedance of the first data output circuit being updated in accordance with the calibration code responsive to the first update command, and impedance of the second data output circuit being updated in accordance with the calibration code responsive to the second update command.

13. The apparatus of claim 10 , further comprising a second memory device including a third channel comprising a fifth command terminal coupled to the first command terminal, a fifth data terminal coupled to the first data terminal and a third data output circuit coupled to the fifth data terminal, a fourth channel comprising a sixth command terminal coupled to the second command terminal, a sixth data terminal coupled to the second data terminal and a fourth data output circuit coupled to the sixth data terminal, and an additional calibration circuit configured to provide an additional calibration code responsive to each of the first calibration command and the second calibration command.

14. The apparatus of claim 13 , further comprising an additional reference resistor, wherein the second memory device includes an additional calibration terminal coupled between the additional reference resistor and the additional calibration circuit.

15. An apparatus comprising:
a calibration circuit configured to generate a calibration code responsive to a command signal;
an arbiter configured to be supplied with a first calibration command and a second calibration command independently of each other and arbitrate the first calibration command and the second calibration command to provide the command signal; and
a first relay circuit configured to store the calibration code responsive to a first update command and a second relay circuit configured to store the calibration code responsive to a second update command.

16. The apparatus of claim 15 , wherein the arbiter is configured not to provide the command signal responsive to the second calibration command on condition that the calibration circuit is in a calibration operation executed responsive to the first calibration command.

17. The apparatus of claim 16 , wherein the arbiter is configured not to provide the command signal responsive to the first calibration command on condition that the calibration circuit is in the calibration operation executed responsive to the second calibration command.

18. The apparatus of claim 15 , further comprising a first data output circuit configured to change i

Assignees

• Micron Technology Inc

Inventors

• Arai Tetsuya
• Taniguchi Junki

Classifications

• H03K19/018507

  Interface arrangements · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title