Optoelectronic component with current deflected to high-gain paths comprising an avalanche photodiode having an absorbing region on a p-doped lateral boundary, an n-doped lateral boundary and an amplifying region

Patent metadata

Field	Value
Publication number	US-10854768-B2
Application number	US-201816226753-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A three-terminal avalanche photodiode provides a first controllable voltage drop across a light absorbing region and a second, independently controllable, voltage drop across a photocurrent amplifying region. The absorbing region may also have a different composition from the amplifying region, allowing further independent optimization of the two functional regions. An insulating layer blocks leakage paths, redirecting photocurrent toward the region(s) of highest avalanche gain. The resulting high-gain, low-bias avalanche photodiodes may be fabricated in integrated optical circuits using commercial CMOS processes, operated by power supplies common to mature computer architecture, and used for optical interconnects, light sensing, and other applications.

First claim

We claim:

1. An avalanche photodiode comprising:
an amplifying region on a substrate;
a p-doped lateral boundary on a first side of the amplifying region;
a first terminal coupled to the p-doped lateral boundary;
an n-doped lateral boundary on a second side of the amplifying region;
a second terminal coupled to the n-doped lateral boundary;
an absorbing region on the p-doped lateral boundary, the n-doped lateral boundary, and the amplifying region;
a third terminal coupled to the absorbing region; and
an insulating layer between the absorbing region and the n-doped lateral boundary.

2. The avalanche photodiode of claim 1 , further comprising a p-doped contact region between the absorbing region and the third terminal.

3. The avalanche photodiode of claim 1 , further comprising an undoped layer between the substrate and a shared bottom surface of the p-doped lateral boundary, the n-doped lateral boundary, and the amplifying region.

4. The avalanche photodiode of claim 1 , further comprising an undoped layer between the absorbing region and a shared top surface of the p-doped lateral boundary, the n-doped lateral boundary, and the amplifying region.

5. The avalanche photodiode of claim 1 , wherein the substrate comprises a silicon-on-insulator wafer.

6. The avalanche photodiode of claim 1 , wherein the amplifying region between the p-doped lateral boundary and the n-doped lateral boundary is 100-500 nanometers wide.

7. The avalanche photodiode of claim 1 , wherein the amplifying region comprises silicon, and the absorbing region comprises germanium.

8. The avalanche photodiode of claim 1 , wherein the insulating layer comprises at least one of an oxide, a nitride, a polymer, or a doped region.

9. The avalanche photodiode of claim 1 , wherein the insulating layer is 8-12 nm thick.

10. A method of fabricating an optoelectronic component, the method comprising:
p-doping a semiconductor to form a first contact and a p-doped lateral boundary for an amplifying region;
n-doping the semiconductor to form a second contact and an n-doped lateral boundary for an amplifying region;
forming an insulating layer over the n-doped lateral boundary;
forming an absorbing region over the p-doped lateral boundary, the n-doped lateral boundary, and the amplifying region;
p-doping the absorbing region to form a third contact; and
forming connections to the first contact, the second contact, and the third contact.

11. The method of claim 10 , wherein the semiconductor comprises a native silicon layer of a silicon-on-insulator substrate.

12. The method of claim 10 , wherein the p-doping of the semiconductor further comprises forming at least one additional p-doped lateral boundary, and the n-doping of the semiconductor further comprises forming at least one additional n-doped lateral boundary.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Zeng Xiaoge
• Huang Zhihong
• Liang Di

Classifications

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F77/14

  Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies · CPC title

• H10F30/2255 Primary

  in which the active layers form heterostructures, e.g. SAM structures · CPC title

• H10F30/225 Primary

  the potential barrier working in avalanche mode, e.g. avalanche photodiodes · CPC title

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title