Image processor complex transfer functions

Patent metadata

Field	Value
Publication number	US-10853908-B2
Application number	US-202016779257-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Feb 12, 2019
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting complex transfer functions on an image processor. One of the methods includes traversing, by each execution lane of an image processor using a shift-register array, a respective local support region and storing input pixels encountered during the traversal into local memory of the image processor. Each execution lane obtains from the local memory of the image processor one or more input pixels according to a complex transfer function. Each execution lane computes a respective output pixel for the kernel program using one or more input pixels obtained from the local memory according to the complex transfer function.

First claim

What is claimed is:

1. A computer-implemented method comprising:
loading data within an input image region into a two-dimensional shift-register array of an image processor;
computing a local support region size needed to obtain input pixels required to compute each respective output pixel in an output image region;
traversing, by each of a plurality of execution lanes using the two-dimensional shift-register array, a respective local support region having the computed local support region size and storing input pixels encountered during the traversal into local memory of the image processor;
obtaining, by each execution lane from the local memory of the image processor, one or more respective input pixels required to compute a respective output pixel by the execution lane; and
computing, by each execution lane, a respective output pixel using one or more respective input pixels obtained from the local memory.

2. The method of claim 1 , wherein the method comprises executing instructions that define how to compute an output image region from an input image region.

3. The method of claim 1 , wherein the method comprises executing instructions that define a complex transfer function that specifies how to compute locations of the one or more input pixels required to compute the respective output pixel in an output image region.

4. The method of claim 1 , wherein traversing the respective local support region comprises shifting data in the two-dimensional shift-register array according to a pattern corresponding to a shape of the local support region.

5. The method of claim 4 , wherein traversing the respective local support region comprises:
computing, by each execution lane, a respective size of a local bounding box based on a maximum distance between the output pixel and each input pixel needed to compute the output pixel; and
traversing the local bounding box.

6. The method of claim 1 , wherein obtaining, by each execution lane from the local memory of the image processor, one or more respective input pixels required to compute a respective output pixel by the execution lane comprises:
computing, by each execution lane according to a complex transfer function, an offset of data needed to obtain the one or more input pixels from the local memory to compute the respective output pixel for the execution lane; and
loading, by each execution lane, the one or more input pixels from the local memory using the computed offset.

7. The method of claim 1 , wherein loading data within the input image region into the two-dimensional shift-register array comprises:
computing a global support region needed to compute the output image region from the input image region; and
loading data within the global support region into the two-dimensional shift-register array.

8. The method of claim 1 , wherein the local memory has one-dimensional direct addressing.

9. The method of claim 1 , further comprising computing a global support region needed to compute the output region for a kernel program including computing one or more corners of the global support region by executing a complex transfer function and providing, to the complex transfer function, one or more pairs of coordinates of one or more corners of the output region.

10. A computing device employing an image processor, the image processor comprising an execution lane array and a two-dimensional shift-register array,
wherein the image processor is configured to execute instructions to perform operations comprising:
loading data within an input image region into a two-dimensional shift-register array;
computing a local support region size needed to obtain input pixels required to compute each respective output pixel in an output image region;
traversing, by each of a plurality of execution lanes using the two-dimensional shift-register array, a respective local support region having the computed local support region size and storing input pixels encountered during the traversal into local memory of the image processor;
obtaining, by each execution lane from the local memory of the image processor, one or more respective input pixels required to compute a respective output pixel by the execution lane; and
computing, by each execution lane, a respective output pixel using one or more respective input pixels obtained from the local memory.

11. The computing device of claim 10 , wherein the instructions define how to compute an output image region from an input image region.

12. The computing device of claim 10 , wherein the instructions define a complex transfer function that specifies how to compute locations of the one or more input pixels required to compute the respective output pixel in an output image region.

13. The computing device of claim 10 , wherein traversing the respective local support region comprises shifting data in the two-dimensional shift-register array according to a pattern corresponding to a shape of the local support region.

14. The computing device of claim 13 , wherein traversing the respective local support region comprises:
computing, by each execution lane, a respective size of a local bounding box based on a maximum distance between the output pixel and each input pixel needed to compute the output pixel; and
traversing the local bounding box.

15. The computing device of claim 10 , wherein obtaining, by each execution lane from the local memory of the image processor, one or more respective input pixels required to compute a respective output pixel by the execution lane comprises:
computing, by each execution lane according to a complex transfer function, an offset of data needed to obtain the one or more input pixels from the local memory to compute the respective output pixel for the execution lane; and
loading, by each execution lane, the one or more input pixels from the local memory using the computed offset.

16. The computing device of claim 10 , wherein loading data within the input image region into the two-dimensional shift-register array comprises:
computing a global support region needed to compute the output image region from the input image region; and
loading data within the global support region into the two-dimensional shift-register array.

17. The computing device of claim 10 , wherein the local memory has one-dimensional direct addressing.

18. The computing device of claim 10 , wherein the operations further comprise computing a global support region needed to compute the output region for a kernel program including computing one or more corners of the global support region by executing a complex transfer function and providing, to the complex transfer function, one or more pairs of coordinates of one or more corners of the output region.

19. One or more non-transitory computer storage media encoded with computer program instructions that when executed by an image processor comprising an execution lane array and a two-dimensional shift-register array, causes the image processor to perform operations comprising:
loading data within an input image region into a two-dimensional shift-register array;
computing a local support region size needed to obtain input pixels required to compute each respective output pixel in an output image region;
traversing, by each of a plurality of execution lanes using the two-dimensional shift-register array, a respective local support region having the computed local support region size and storing input pixels encountered during the traversal into local memory of the image processor;
obtaining,

Assignees

• Google Llc

Inventors

• Meixner Albert

Classifications

• G06T3/40

  Scaling of whole images or parts thereof, e.g. expanding or contracting · CPC title

• G06T2210/52

  Parallel processing · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T2200/28

  involving image processing hardware · CPC title