Method of making ohmic contact on low doped bulk silicon for optical alignment

Patent metadata

Field	Value
Publication number	US-10850976-B2
Application number	US-201916515325-A
Country	US
Kind code	B2
Filing date	Jul 18, 2019
Priority date	Sep 21, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip including an epitaxial layer overlying a microelectromechanical systems (MEMS) substrate. The method includes bonding a MEMS substrate to a carrier substrate, the MEMS substrate includes monocrystalline silicon. An epitaxial layer is formed over the MEMS substrate, the epitaxial layer has a higher doping concentration than the MEMS substrate. A plurality of contacts are formed over the epitaxial layer, the plurality of contacts respectively form ohmic contacts with the epitaxial layer.

First claim

What is claimed is:

1. A method for manufacturing a microelectromechanical systems (MEMS) structure, the method comprising:
bonding a MEMS substrate to a carrier substrate, wherein the MEMS substrate comprises monocrystalline silicon;
forming an epitaxial layer over the MEMS substrate, wherein the epitaxial layer has a higher doping concentration than the MEMS substrate; and
forming a plurality of contacts over the epitaxial layer, wherein the plurality of contacts respectively from ohmic contacts with the epitaxial layer.

2. The method according to claim 1 , further comprising:
performing an etching process to define at least one moveable element in the MEMS substrate and a cavity between an upper surface of the carrier substrate and a top surface of the epitaxial layer, wherein the at least one moveable element is within the cavity, and wherein at least one contact from the plurality of contacts overlies the at least one moveable element.

3. The method according to claim 1 , wherein formation of the plurality of contacts comprises:
forming a silicon layer over the epitaxial layer;
forming a metal layer over the silicon layer; and
performing an annealing process to convert the silicon layer into a silicide layer, wherein an ohmic contact exists between the metal layer and the epitaxial layer through the silicide layer; and
performing an etching process to define the plurality of contacts.

4. The method according to claim 3 , further comprising:
forming a sacrificial metal layer over the silicon layer before forming the metal layer;
wherein the annealing process converts the silicon layer and the sacrificial metal layer into the silicide layer, wherein the sacrificial metal layer comprises a metal different from a metal the metal layer is comprised of.

5. The method according to claim 3 , wherein a bottom surface of the silicide layer is vertically below a top surface of the epitaxial layer and a top surface of the silicide layer is vertically above the top surface of the epitaxial layer.

6. The method according to claim 1 , wherein formation of the plurality of contacts comprises:
forming a passivation layer over the epitaxial layer;
forming a plurality of metal vias through the passivation layer, wherein the plurality of vias directly contact a top surface of the epitaxial layer;
forming a metal layer over the passivation layer; and
performing an etching process into the metal layer to define the plurality of contacts, wherein each metal via underlies a contact in the plurality of contacts.

7. The method according to claim 6 , further comprising:
performing an annealing process after forming the plurality of metal vias such that a silicide layer of a material the plurality of metal vias forms below the top surface of the epitaxial layer under each metal via.

8. The method according to claim 6 , wherein the plurality of metal vias comprise a first material different than a second material the metal layer is comprised of.

9. The method according to claim 1 , wherein the MEMS substrate comprises intrinsic monocrystalline silicon.

10. A method for manufacturing an integrated chip, the method comprising:
forming a plurality of alignment regions over a first substrate;
bonding the first substrate to a second substrate to form a cavity between the first substrate and the second substrate;
performing a thinning process on the second substrate;
forming an epitaxial layer over the second substrate, wherein the epitaxial layer has a higher doping concentration than the second substrate;
forming a plurality of contacts over a top surface of the epitaxial layer, wherein the forming process includes aligning the plurality of contacts over the first substrate by virtue of the plurality of alignment regions by using near-infrared (NIR) light illuminated from the top surface of the epitaxial layer to the plurality of alignment regions; and
performing an etching process to remove a portion of the second substrate and the epitaxial layer directly above the cavity and define at least one movable element, wherein a first subset of the plurality of contacts are directly over the at least one movable element.

11. The method according to claim 10 , wherein a second subset of the plurality of contacts are arranged laterally outside the cavity, a minimum width of the plurality of contacts within the second subset is at least two times greater than a maximum width of the plurality of contacts within the first subset.

12. The method according to claim 10 , wherein the NIR light is used to align a photomask that is used to perform the etching process by virtue of the plurality of alignment regions.

13. The method according to claim 10 , wherein the plurality of contacts respectively form ohmic contacts with the epitaxial layer.

14. The method according to claim 10 , wherein the NIR light is illuminated from above the top surface of the epitaxial layer to a bottom surface of the first substrate.

15. The method according to claim 10 , wherein a second plurality of alignment regions are formed on the second substrate before forming the epitaxial layer, wherein any alignment by virtue of the plurality of alignment regions concurrently utilizes the second plurality of alignment regions.

16. The method according to claim 10 , wherein at least one alignment region in the plurality of alignment regions is formed on a lower surface of the cavity.

17. A method for manufacturing an integrated chip, the method comprising:
forming a plurality of alignment marks on a carrier substrate;
bonding the carrier substrate to a microelectromechanical systems (MEMS) substrate to form a cavity between the carrier substrate and the MEMS substrate, wherein the bonding process includes aligning the MEMS substrate over the carrier substrate by virtue of the plurality of alignment marks by using infrared (IR) light;
performing a thinning process on the MEMS substrate;
forming an epitaxial layer over the MEMS substrate such that a resistance of the of the epitaxial layer is less than a resistance of the MEMS substrate;
forming a plurality of contacts over a top surface of the epitaxial layer, wherein forming the plurality of contacts includes aligning the plurality of contacts over the carrier substrate by virtue of the plurality of alignment marks by using IR light illuminated from the top surface of the epitaxial layer to the plurality of alignment marks;
performing an etching process to remove a portion of the MEMS substrate and the epitaxial layer above the cavity and form at least one movable element, wherein a first subset of the plurality of contacts are directly over the at least one movable element; and
bonding the plurality of contacts to an interconnect structure of an integrated circuit (IC) die.

18. The method of claim 17 , wherein the resistance of the epitaxial layer is within a range of about 1 to 5 milliohms centimeter.

19. The method of claim 17 , wherein bonding the carrier substrate to the MEMS substrate includes performing a fusion bond.

20. The method of claim 17 , wherein the plurality of alignment marks are laterally offset from the plurality of contacts by one or more non-zero distances.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Kuei-Sung
• Chu Chia-Hua
• Tsai Shang-Ying

Classifications

• B81C2201/019

  Bonding or gluing multiple substrate layers · CPC title

• B81B7/0006

  Interconnects · CPC title

• B81C1/00198 Primary

  comprising elements which are movable in relation to each other, e.g. comprising slidable or rotatable elements · CPC title

• B81B5/00

  Devices comprising elements which are movable in relation to each other, e.g. comprising slidable or rotatable elements · CPC title

• B81C1/00095 Primary

  Interconnects · CPC title