Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2017129772-A1
Application number	US-201715407676-A
Country	US
Kind code	A1
Filing date	Jan 17, 2017
Priority date	Nov 6, 2015
Publication date	May 11, 2017
Grant date	—

Abstract

A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first device; a second device, contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole, disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole, disposed in the second device and aligned to the first hole; and a sealing object, for sealing the second hole; wherein the first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

2 . The semiconductor structure of claim 1 , wherein the first device is a complementary metal oxide semiconductor (CMOS) device and the second device is a micro-electro mechanical system (MEMS) device.

3 . The semiconductor structure of claim 1 , wherein the first device is a micro-electro mechanical system (MEMS) device and the second device is a complementary metal oxide semiconductor (CMOS) device.

4 . The semiconductor structure of claim 1 , wherein the sealing object comprises:
an oxide layer, disposed over the second hole for sealing the third end; and a metal layer, disposed over the oxide layer.

5 . The semiconductor structure of claim 4 , wherein the metal layer further disposes over an outer surface of the second device.

6 . The semiconductor structure of claim, wherein the first hole and the second hole are cylindrical profile.

7 . The semiconductor structure of claim 1 , wherein the first hole and the second hole have a first depth and a second depth respectively, and the first depth is smaller than the second depth.

8 . The semiconductor structure of claim 1 , wherein the sealing object is arranged to seal the third end of the second hole.

9 . The semiconductor structure of claim 1 , wherein a self-assembled monolayer (SAM) coating is deposited on a surface of the chamber.

10 . A method of fabricating a semiconductor structure, comprising.
providing a first device; providing a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; forming a first hole in the second device and defined between a first end with a first circumference and a second end with a second circumference; forming a second hole in the second device and aligned to the first hole; and sealing the second hole by using a sealing object; wherein the first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

11 . The method of claim 10 , herein sealing the second hole by using the sealing object comprises:
forming an oxide layer over the second hole for sealing the third end; and forming a metal layer over the oxide layer.

12 . The method of claim 11 , wherein sealing the second hole by using the sealing object further comprises:
disposing the metal layer over an outer surface of the second device.

13 . The method of claim 10 , wherein the first hole and the second hole are cylindrical profile.

14 . The method of claim 10 , wherein the first hole and the second hole have a first depth and a second depth respectively, and the first depth is smaller than the second depth.

15 . The method of claim 10 , wherein sealing the second hole by using the sealing object comprises:
sealing the second hole from the third end of the second hole.

16 . The method of claim 10 , further comprising:
performing a SAM coating upon a surface of the chamber via the second hole.

17 . A semiconductor structure, comprising:
a semiconductor device; a cap wafer, disposed over the semiconductor device, wherein a chamber is formed between the semiconductor device and the cap wafer; a first hole, disposed in the cap wafer and defined between a first end with a first circumference and a second end with a second circumference; a second hole, disposed in the cap wafer and aligned to the first hole; and a sealing object, for sealing the second hole; wherein the first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.

18 . The semiconductor structure of claim 17 , wherein the sealing object comprises:
an oxide layer, disposed over the second hole for sealing the third end; and a metal layer, disposed over the oxide layer.

19 . The semiconductor structure of claim 18 , wherein the metal layer further disposes over an outer surface of the cap wafer.

20 . The semiconductor structure of claim 17 , wherein the first hole and the second hole have a first depth and a second depth respectively, and the first depth is smaller than the second depth.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chun-Wen
• Teng Yi-Chuan
• Hsieh Cheng-Yu
• Tseng Lee-Chuan
• Liu Shih-Chang
• Lin Shih-Wei

Classifications

• B81C1/00285

  using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters · CPC title

• B81B2207/012

  the micromechanical device and the control or processing electronics being separate parts in the same package · CPC title

• B81B7/008 Primary

  MEMS characterised by an electronic circuit specially adapted for controlling or driving the same (B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00) · CPC title

• B81C2203/0792

  Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

• B81B7/0035 Primary

  for maintaining a controlled atmosphere inside of the chamber containing the MEMS · CPC title