Apparatus and method for timestamping of data packets

Patent metadata

Field	Value
Publication number	US-10848257-B2
Application number	US-201916580270-A
Country	US
Kind code	B2
Filing date	Sep 24, 2019
Priority date	May 15, 2015
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

An apparatus and method for timestamping data packets are provided. The apparatus includes an input bit counter responsive to input bits entering a physical layer (PHY) device and an output bit counter responsive to output bits transmitted by the PHY device. A timestamp for an incoming bit is calculated based on a number of bits awaiting transmission by the PHY device at the time of arrival of the incoming bit. The number of bits awaiting transmission by the PHY device is determined based on the first count and the second count.

First claim

What is claimed is:

1. A communications device, comprising:
a physical layer (PHY) device having an input port and an output port, the input port configured to receive data from a physical medium; and
control circuitry configured to:
generate a first timestamp for a first bit of a beat of data upon generation of the first bit by the PHY device on the output port of the PHY device; and
determine that the beat of data includes a first bit of a data packet, wherein the first bit of the data packet is offset from the first bit of the beat of data;
determine a bit shift of the first bit of the data packet relative to the first bit of the beat of data;
calculate a second timestamp for the first bit of the data packet based on the first timestamp and the determined bit shift, wherein the second time stamp indicates a time of reception of the first bit of the data packet by a physical medium dependent (PMD) sublayer of the PHY device; and
forward the second time stamp and the data packet to one or more layers of the communications device that is above the PHY layer.

2. The communications device of claim 1 , wherein the control circuitry is further configured to determine the bit shift as the bit location of the first bit of the data packet relative to the first bit of the beat of data.

3. The communications device of claim 2 , wherein the control circuitry is further configured to calculate a first latency required to receive, by the PMD sublayer, bits preceding the first bit of the data packet within the beat of data based on the bit location of the first bit of the data packet within the beat of data and a predetermined receive latency of the PMD sublayer.

4. The communications device of claim 3 , wherein the control circuitry is further configured to calculate a second latency required to receive, by the PMD sublayer, the first bit of the data packet based on the predetermined receive latency of the PMD sublayer.

5. The communications device of claim 4 , wherein the control circuitry is further configured to calculate sum the first time stamp and the first latency and subtract the second latency to determine the second time stamp.

6. The communications device of 1 , wherein the PHY devices includes multiple data receive lanes having corresponding PMD sublayers, and wherein the control circuitry is further configured to determine time stamps that indicate a time of reception of first bits of corresponding data packets received by each of the PMD sublayers of the PHY device.

7. A method of processing data packets, comprising:
receiving, by a physical layer (PHY) device, data from a physical medium;
generating a first timestamp for a first bit of a beat of data upon generation of the first bit by the PHY device on an output port of the PHY device; and
determining that the beat of data includes a first bit of a data packet, wherein the first bit of the data packet is offset from the first bit of the beat of data;
determining a bit shift of the first bit of the data packet relative to the first bit of the beat of data;
calculating a second timestamp for the first bit of the data packet based on the first timestamp and the determined bit shift; and
forwarding the second time stamp and the data packet to one or more layers of a communications device that are above the PHY layer.

8. The method of claim 7 , wherein the second time stamp indicates a time of reception of the first bit of the data packet by a physical medium dependent (PMD) sublayer of the PHY device.

9. The method of claim 8 , wherein the bit shift is determined as the bit location of the first bit of the data packet relative to the first bit of the beat of data.

10. The method of claim 9 , further comprising calculating a first latency required to receive, by the PMD sublayer, bits preceding the first bit of the data packet within the beat of data based on the bit location of the first bit of the data packet within the beat of data and a predetermined receive latency of the PMD sublayer.

11. The method of claim 10 , further comprising calculating a second latency required to receive, by the PMD sublayer, the first bit of the data packet based on the predetermined receive latency of the PMD sublayer.

12. The method of claim 11 , wherein the calculating the second time stamp includes:
summing the first time stamp and the first latency and subtracting the second latency.

13. A communications device, comprising:
a physical layer (PHY) device having an input port and an output port, the input port configured to receive data from a physical medium; and control circuitry configured to:
generate a first timestamp for a first bit of a beat of data upon generation of the first bit by the PHY device on the output port; and
when the beat of data includes a first bit of a data packet,
determine a bit shift of the first bit of the data packet from the first bit of the beat of data; and
calculate a second timestamp for the first bit of the data packet based on the first timestamp and the determined bit shift;
wherein the control circuitry is further configured to forward the second time stamp and the data packet to one or more layers that are above the PHY layer.

14. The communications device of claim 13 , wherein the control circuitry is further configured to:
determine whether the beat of data includes a boundary bit of a data block; and
when the beat of data includes the boundary bit of the data block, determine a third timestamp for the boundary bit based on the first timestamp and a bit location of the boundary bit within the beat of data.

15. The communications device of claim 14 , wherein the control circuitry is further configured to:
determine whether the data block corresponds to a first data block of the data packet; and
when the data block corresponds to the first data block of the data packet, set the bit shift of the first bit of the data packet as equal to the bit location of the boundary bit within the beat of data.

16. The communications device of claim 15 , wherein the control circuitry is further configured to calculate a first latency required to receive, by the PHY device, bits preceding the boundary bit within the beat of data based on the bit location of the boundary bit within the beat of data.

17. The communications device of claim 16 , wherein the control circuitry is further configured to calculate a second latency required to receive, by the PHY device, the boundary bit based on a pre-determined bit receive rate of the PHY device.

18. The communications device of claim 17 , wherein the control circuitry is further configured to calculate the second timestamp for the first bit of the data packet as a sum of the first timestamp and the first latency, minus the second latency.

19. The method of claim 13 , wherein the second time stamp indicates a time of reception of the first bit of data by a physical medium dependent (PMD) sublayer of the PHY device.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Baden Eric
• Bansal Ankit
• Gargeshwari Sharath

Classifications

• H04L43/0894

  Packet rate · CPC title

• H04J3/0661

  using timestamps · CPC title

• H04J3/0697 Primary

  Synchronisation in a packet node · CPC title

• H04L43/0852

  Delays · CPC title

• H04L69/28

  Timers or timing mechanisms used in protocols · CPC title