Forcing and sensing DACs sharing reference voltage

Patent metadata

Field	Value
Publication number	US-10848172-B2
Application number	US-201916704497-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	Mar 4, 2019
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.

First claim

The claimed invention is:

1. A device or assembly including an integrated circuit comprising:
reference voltage buffer circuitry, including an amplifier circuit, providing a commonly-routed amplifier shared output voltage node that is shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes located at corresponding DACs; and
wherein the first and second individually routed traces are configured with respective first and second routing resistances that are based on an expected or measured current loading from the corresponding DAC to provide an equal voltage drop across the first and second routing resistances for avoiding voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes.

2. The device or assembly of claim 1 , further comprising:
at least two switches corresponding to the at least two DACs, wherein each switch is positioned in series with its corresponding DAC, and wherein each switch is configured to be closed when its corresponding DAC is ON.

3. The device or assembly of claim 2 , wherein the at least two switches are first switches, the device or assembly further comprising:
at least two feedback paths coupled between corresponding ones of the respective first and second local reference voltage nodes and the amplifier circuit; and
at least two second switches positioned within corresponding ones of the at least two feedback paths, wherein each second switch is configured to be closed when its corresponding DAC is ON.

4. The device or assembly of claim 2 , the device or assembly further comprising:
a feedback path coupled between the first local reference voltage node and the amplifier circuit; and
a current source coupled to the feedback path.

5. The device or assembly of claim 4 , wherein the current source is a replica DAC.

6. The device or assembly of claim 1 , wherein the at least two DACs include resistor string DACs.

7. The device or assembly of claim 1 , wherein at least one of the first and second individually routed traces includes a binary tree hierarchical routing arrangement of at least some of the at least two DACs.

8. In a device or assembly including an integrated circuit having reference voltage buffer circuitry including an amplifier circuit, a method of avoiding voltage contention or conflict at a commonly-routed amplifier shared output voltage node that is shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes located at corresponding DACs, the method comprising:
forming the first and second individually routed traces with respective first and second routing resistances that are based on an expected or measured current loading from the corresponding DAC to provide an equal voltage drop across the first and second routing resistances for avoiding voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes.

9. The method of claim 8 , wherein forming the first and second individually routed traces with respective first and second routing resistances comprises:
adjusting a linewidth of at least one of the first and second individually routed traces.

10. The method of claim 8 , wherein forming the first and second individually routed traces with respective first and second routing resistances comprises:
adjusting a length of at least one of the first and second individually routed traces.

11. The method of claim 8 , further comprising:
controlling a switch corresponding to one of the at least two DACs to be open when its corresponding DAC is OFF, wherein the switch is positioned in series with its corresponding DAC.

12. The method of claim 11 , wherein the switch is a first switch, the method further comprising:
forming at least two feedback paths between corresponding ones of the respective first and second local reference voltage nodes and the amplifier circuit; and
controlling a second switch positioned within a corresponding one of the at least two feedback paths to be open when its corresponding DAC is OFF.

13. The method of claim 11 , wherein the switch is a first switch, the method further comprising:
forming a feedback path between the first local reference voltage node and the amplifier circuit; and
controlling a current source coupled to the feedback path to be ON regardless of a power state of the at least two DACs.

14. The method of claim 13 , wherein controlling a current source coupled to the feedback path to be ON regardless of a power state of the at least two DACs includes:
controlling a replica DAC coupled to the feedback path to be ON regardless of a power state of the at least two DACs.

15. The method of claim 8 , wherein the at least two DACs include resistor string DACs.

16. The method of claim 8 , wherein at least one of the first and second individually routed traces includes a binary tree hierarchical routing arrangement of at least some of the at least two DACs.

17. A device or assembly including an integrated circuit comprising:
buffer circuitry having an output voltage node that is shared between two resistor string digital-to-analog converters (DACs) respectively via first and second individually routed traces from the output voltage node to respective first and second local reference voltage nodes located at corresponding DACs; and
wherein the first and second individually routed traces are configured with respective first and second routing resistances that are based on a determined current loading from the corresponding DAC to provide an equal voltage drop across the first and second routing resistances for avoiding voltage contention at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes.

18. The device or assembly of claim 17 , further comprising:
at least two switches corresponding to the at least two DACs, wherein each switch is positioned in series with its corresponding DAC, and wherein each switch is configured to be closed when its corresponding DAC is ON.

19. The device or assembly of claim 18 , wherein the at least two switches are first switches, the device or assembly further comprising:
at least two feedback paths coupled between corresponding ones of the respective first and second local reference voltage nodes and the amplifier circuit; and
at least two second switches positioned within corresponding ones of the at least two feedback paths, wherein each second switch is configured to be closed when its corresponding DAC is ON.

20. The device or assembly of claim 19 , the device or assembly further comprising:
a feedback path coupled between the first local reference voltage node and the amplifier circuit; and
a current source coupled to the feedback path.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Ramalingam Kirubakaran
• Das Ayan
• Mathukkarumukku Hrishikesh Ravi
• Kumbaranthodiyil Mahesh Madhavan

Classifications

• H03M1/808

  using resistors · CPC title

• H03M1/76 Primary

  using switching tree · CPC title

• H03M1/1042 Primary

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/0609

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error · CPC title