Buried low-resistance metal word lines for cross-point variable-resistance material memories

Patent metadata

Field	Value
Publication number	US-10847722-B2
Application number	US-201816128052-A
Country	US
Kind code	B2
Filing date	Sep 11, 2018
Priority date	Sep 19, 2007
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

First claim

What is claimed is:

1. A memory structure, comprising:
a semiconductive substrate, wherein the semiconductive substrate includes a pillar that is isolated from an adjacent pillar by a shallow trench isolation (STI) structure;
an epitaxial first film disposed on an upper surface of the pillar;
an epitaxial second film disposed above and on the epitaxial first film, forming a diode over the pillar by the epitaxial first film and the epitaxial second film;
a variable-resistance material coupled to the diode; and
a salicide word line having at least a portion disposed below the epitaxial first film and in the pillar, the salicide word line having a surface coplanar with an outer surface of a portion of the pillar, and an upper portion of the pillar including the upper surface of the pillar extending above and over a portion of a top surface of the salicide word line.

2. The memory structure of claim 1 , further comprising a spacer disposed over the salicide word line.

3. The memory structure of claim 1 , further comprising a buried oxide layer that fills an undercut in the pillar.

4. The memory structure of claim 1 , further comprising
a spacer disposed above the salicide word line; and
a buried oxide layer that fills an undercut in the pillar.

5. The memory structure of claim 1 , wherein the salicide word line comprises cobalt silicide.

6. The memory structure of claim 1 , wherein the variable-resistance material comprises a phase-change material.

7. The memory structure of claim 1 , wherein the variable-resistance material is selected from an alloy, a quasi-metal composition, a metal oxide, and a chalcogenide.

8. The memory structure of claim 1 , wherein the variable-resistance material comprises a gallium containing material, a germanium containing material, an indium containing material, as antimony containing material, a tellurium containing material, a selenium containing material, an arsenic containing material, an aluminum containing material, a tin containing material, a palladium containing material, a silver containing material, or a colossal magnetoresistive film.

9. The memory structure of claim 1 , wherein the variable-resistance material comprises a doped chalcogenide glass of the general formula AxBy, B selected from sulfur, selenium, and tellurium, and mixtures thereof, and A includes at least one element from Group III-A, Group IV-A, Group V-A, or Group VII-A of the periodic table.

10. The memory structure of claim 9 , wherein the doped chalcogenide glass comprises one or more dopants selected from noble metal elements and transition metal elements.

11. The memory structure of claim 1 , wherein the variable-resistance material is disposed between a top electrode and a bottom electrode.

12. The memory structure of claim 11 , wherein the bottom electrode comprises one of titanium nitride, titanium aluminum nitride, titanium nickel tin, tantalum nitride, or tantalum silicon nitride.

13. The memory structure of claim 11 , wherein the bottom electrode electrically and directly connected to a silicide contact that is directly connected to the diode.

14. The memory structure of claim 11 , further comprising a bit line coupled to the variable-resistance material.

15. The memory structure of claim 14 , wherein the bit line is coupled to the variable-resistance mated al via the top electrode.

16. A device, comprising:
a first device component; and
multiple variable-resistance structures coupled to the first device component, each variable-resistance structure comprising:
a semiconductive substrate, the semiconductive substrate comprising a pillar isolated from an adjacent pillar by a shallow trench isolation (STI) structure;
a diode over the pillar, the diode comprising an epitaxial first film disposed on an upper surface of the pillar, and an epitaxial second film disposed on the epitaxial first film;
a variable-resistance material above and coupled to the diode; and
a salicide word line extending within the pillar and separated from an adjacent salicide word line within the pillar, the salicide word line having at least a portion disposed below the epitaxial first film, and having a surface coplanar with an outer vertical surface of a portion of the pillar, and an upper portion of the pillar including the upper surface of the pillar extending above and over a top surface of the salicide word line.

17. The device of claim 16 , wherein the variable-resistance material is selected from an alloy, a quasi-metal composition, a metal oxide, and a chalcogenide.

18. The device of claim 16 , herein the variable-resistance material includes a phase-change material.

19. The device of claim 16 , wherein the first device component comprises a processor.

20. The device of claim 16 , wherein the variable-resistance material of each of the multiple variable-resistance structures is coupled to a bit line.

Assignees

• Micron Technology Inc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• H10N70/8836

  Complex metal oxides, e.g. perovskites, spinels · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/8825

  Selenides, e.g. GeSe · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title