Methods of manufacturing integrated circuits using isotropic and anisotropic etching processes

US10847711B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10847711-B2
Application numberUS-201816202496-A
CountryUS
Kind codeB2
Filing dateNov 28, 2018
Priority dateDec 4, 2017
Publication dateNov 24, 2020
Grant dateNov 24, 2020

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Abstract

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A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.

First claim

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What is claimed is: 1. A method of fabricating a magnetoresistive device, comprising: etching a magnetoresistive stack using a first etching process to form one or more first sidewalls, wherein the magnetoresistive stack includes at least an intermediate region formed between a magnetically fixed region and a magnetically free region; etching the magnetoresistive stack using a second etching process after forming the one or more first sidewalls, wherein the second etching process is relatively more isotropic than the first etching process and removes at least a portion of etched material redeposited on one or more second sidewalls; depositing a first encapsulant on the magnetoresistive stack, after forming the one or more first sidewalls and before the step of etching the magnetoresistive stack using the second etching process; and etching the magnetoresistive stack using the first etching process to form the one or more second sidewalls, after the step of depositing the first encapsulant and before the step of etching the magnetoresistive stack using the second etching process. 2. The method of claim 1 , wherein each of the first etching process and the second etching process is one of reactive ion etching (RIE) or ion beam etching (IBE). 3. The method of claim 1 , wherein the first etching process includes a first set of etching parameters, the second etching process includes a second set of etching parameters different from the first set of etching parameters, and wherein each of the first etching process and the second etching process is one of reactive ion etching (RIE) or ion beam etching (IBE). 4. The method of claim 1 , wherein the step of etching the magnetoresistive stack using the first etching process to form the one or more first sidewalls results in etched material being redeposited on the one or more first sidewalls of the magnetoresistive stack. 5. The method of claim 1 , wherein the step of etching the magnetoresistive stack using the first etching process to form the one or more second side walls results in the etched material being redeposited on the one or more second sidewalls of the magnetoresistive stack. 6. The method of claim 1 , further including depositing a second encapsulant on the magnetoresistive stack after etching the magnetoresistive stack using the second etching process. 7. The method of claim 1 , wherein etching the magnetoresistive stack using the first etching process to form the one or more first sidewalls includes terminating the first etching process prior to etching the magnetically fixed region of the magnetoresistive stack. 8. The method of claim 1 , wherein etching the magnetoresistive stack using the first etching process to form the one or more first sidewalls includes terminating the first etching process prior to etching at least one of the magnetically fixed region, the magnetically free region, or the intermediate region of the magnetoresistive stack. 9. The method of claim 1 , wherein the first etching process is at least one of: time-controlled or endpoint-controlled. 10. The method of claim 1 , further including etching the magnetoresistive stack using the second etching process, after forming the one or more first sidewalls and before depositing the first encapsulant on the magnetoresistive stack, wherein the second etching process removes at least a portion of etched material redeposited on the one or more first sidewalls. 11. The method of claim 1 , wherein the first encapsulant comprises an electrically non-conductive material. 12. A method of fabricating a magnetoresistive device including a magnetoresistive stack with at least an intermediate region formed between a magnetically fixed region and a magnetically free region, comprising: etching a first portion of the magnetoresistive stack using a first etching process to form one or more first sidewalls; terminating the first etching process prior to etching at least one of the magnetically fixed region, the magnetically free region, or the intermediate region of the magnetoresistive stack; etching a second portion of the magnetoresistive stack using a second etching process after forming the one or more first sidewalls, wherein the second etching process is relatively more isotropic than the first etching process; depositing a first encapsulant on the magnetoresistive stack before the step of etching the second portion of the magnetoresistive stack using the second etching process; and etching a third portion of the magnetoresistive stack using the first etching process to form one or more second sidewalls, after the step of depositing the first encapsulant and before the step of etching the second portion of the magnetoresistive stack using the second etching process. 13. The method of claim 12 , wherein both the first etching process and the second etching process is one of reactive ion etching (RIE) or ion beam etching (IBE). 14. The method of claim 12 , wherein the first etching process includes a first set of etching parameters, the second etching process includes a second set of etching parameters different from the first set of etching parameters, and wherein each of the first etching process and the second etching process is one of reactive ion etching (RIE) or ion beam etching (IBE). 15. The method of claim 12 , wherein the step of etching the first portion of the magnetoresistive stack using the first etching process results in etched material being redeposited on the one or more first sidewalls of the magnetoresistive stack. 16. The method of claim 12 , wherein the step of etching the third portion of the magnetoresistive stack using the first etching process results in etched material being redeposited on the one or more second sidewalls of the magnetoresistive stack, and wherein the step of etching the second portion of the magnetoresistive stack using the second etching process includes removing at least a portion of the redeposited material from the one or more second sidewalls. 17. The method of claim 12 , further including depositing a second encapsulant on the magnetoresistive stack after etching the second portion of the magnetoresistive stack using the second etching process. 18. The method of claim 12 , wherein the first etching process is terminated prior to etching the magnetically fixed region of the magnetoresistive stack. 19. The method of claim 12 , further including etching a fourth portion of the magnetoresistive stack using the second etching process, after forming the one or more first sidewalls and before the step of depositing the first encapsulant, wherein the fourth portion of the magnetoresistive stack comprises at least in part etched material redeposited on the one or more first sidewalls. 20. The method of claim 12 , wherein the first encapsulant comprises an electrically non-conductive material.

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What does patent US10847711B2 cover?
A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.
Who is the assignee on this patent?
Everspin Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 24 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).