Fast recovery inverse diode

Patent metadata

Field	Value
Publication number	US-10847658-B2
Application number	US-202016883121-A
Country	US
Kind code	B2
Filing date	May 26, 2020
Priority date	Jul 31, 2017
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

An inverse diode die has a high reverse breakdown voltage, a short reverse recovery time Trr, and is rugged in terms of reverse breakdown voltage stability over long term use in hard commutation applications. The die has an unusually lightly doped bottomside P type anode region and also has an N− type drift region above it. Both regions are of bulk wafer material. An N+ type contact region extends down into the drift region. A topside metal electrode is on the contact region. A P type silicon peripheral sidewall region laterally rings around the drift region. A topside passivation layer rings around the topside electrode. A bottomside metal electrode is on the bottom of the die. The die has a deep layer of hydrogen ions that extends through the N− drift region. The die also has a shallow layer of ions. Both ion layers are implanted from the bottomside.

First claim

What is claimed is:

1. A method comprising:
(a) forming a structure in a semiconductor wafer, wherein the wafer has a bottom semiconductor surface and a top semiconductor surface, wherein there is a die area of the semiconductor wafer, wherein the die area has four peripheral side edges, and wherein the structure comprises:
a bottomside P type silicon region that extends upward from the bottom semiconductor surface and that also extends laterally outwardly to the four peripheral side edges of the die area, wherein the bottomside P type silicon region has a P type dopant concentration of less than 8×10 17 atoms/cm 3 ;
an N− type silicon region disposed over the bottomside P type silicon region within the die area;
an N+ type silicon contact region that extends downward from the top semiconductor surface and into the N− type silicon region; and
a P type silicon peripheral sidewall region that laterally rings the N− type silicon region, wherein the P type silicon peripheral sidewall region and the bottomside P type silicon region together are parts of a P type isolation structure that extends from the top semiconductor surface to the bottom semiconductor surface, and wherein each of the N− type silicon region, the N+ type silicon contact region, the P type silicon peripheral sidewall region, and the bottomside P type silicon region is of bulk silicon wafer material;

(b) ion implanting hydrogen ions through the bottom semiconductor surface such that a deep layer of hydrogen ions is formed, wherein the deep layer of hydrogen ions has a distribution disposed about a hydrogen ion local concentration peak surface, and wherein the hydrogen ion local concentration peak surface extends through the N− type silicon region but does not extend through the bottomside P type silicon region;
(c) implanting ions through the bottom semiconductor surface such that a shallow layer of ions is formed, wherein the shallow layer of ions has a distribution disposed about an ion local concentration peak surface, wherein the ion local concentration peak surface is disposed between the deep layer of hydrogen ions and the bottom semiconductor surface, and wherein the ions of the shallow layer of ions are ions taken from the group consisting of hydrogen ions and helium ions; and
(d) forming a topside passivation layer such that the topside passivation layer is disposed over a part of the top semiconductor surface.

2. The method of claim 1 , wherein step (b) and step (c) occur after step (d).

3. The method of claim 1 , wherein step (b) and step (c) occur before step (d).

4. The method of claim 1 , wherein step (b) and step (c) occur after step (a).

5. The method of claim 1 , wherein step (b) and step (c) occur before step (a).

6. The method of claim 1 , wherein an amount of the top semiconductor surface is in contact with the passivation layer after the passivation layer has been formed in (d), and wherein no hydrogen ions and no helium ions are ion implanted through this amount of the top semiconductor surface.

7. The method of claim 1 , wherein the die area has a single PN junction, and wherein the die area includes no semiconductor device other than a diode.

8. A method comprising:
(a) forming a structure in a semiconductor wafer, wherein the wafer has a bottom semiconductor surface and a top semiconductor surface, wherein there is a die area of the semiconductor wafer, wherein the die area has four peripheral side edges, and wherein the structure comprises:
a bottomside P type silicon region that extends upward from the bottom semiconductor surface and that also extends laterally outwardly to the four peripheral side edges of the die area, wherein the bottomside P type silicon region has a P type dopant concentration of less than 8×10 17 atoms/cm 3 ;
an N− type silicon region disposed over the bottomside P type silicon region within the die area;
an N+ type silicon contact region that extends downward from the top semiconductor surface and into the N− type silicon region; and
a P type silicon peripheral sidewall region that laterally rings the N− type silicon region, wherein the P type silicon peripheral sidewall region and the bottomside P type silicon region together are parts of a P type isolation structure that extends from the top semiconductor surface to the bottom semiconductor surface, and wherein each of the N− type silicon region, the N+ type silicon contact region, the P type silicon peripheral sidewall region, and the bottomside P type silicon region is of bulk silicon wafer material;

(b) ion implanting hydrogen ions through the bottom semiconductor surface such that a deep layer of hydrogen ions is formed, wherein the deep layer of hydrogen ions has a distribution disposed about a hydrogen ion local concentration peak surface, and wherein the hydrogen ion local concentration peak surface extends through the N− type silicon region but does not extend through the bottomside P type silicon region;
(c) implanting ions through the bottom semiconductor surface such that a shallow layer of ions is formed, wherein the shallow layer of ions has a distribution disposed about an ion local concentration peak surface,
wherein the ion local concentration peak surface is a planar surface that extends in a plane parallel to the bottom semiconductor surface, wherein the ion local concentration peak surface extends through the bottomside P type silicon region but does not extend through the N− type silicon region, and wherein the ions of the shallow layer of ionscomprises helium ions.

9. The method of claim 8 , further comprising: (d) forming a topside passivation layer such that the topside passivation layer is disposed over a part of the top semiconductor surface.

10. The method of claim 8 , wherein an amount of the top semiconductor surface is in contact with the passivation layer after the passivation layer has been formed in (d), and wherein no hydrogen ions and no helium ions are ion implanted through this amount of the top semiconductor surface.

11. The method of claim 8 , wherein the die area has a single PN junction, and wherein the die area includes no semiconductor device other than a diode.

Assignees

• Ixys Llc
• Littelfuse Inc

Inventors

• Wisotzki Elmar

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W74/47

  comprising organic materials, e.g. plastics or resins · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title