Semiconductor device having metallic source and drain regions

Patent metadata

Field	Value
Publication number	US-10847653-B2
Application number	US-201715408294-A
Country	US
Kind code	B2
Filing date	Jan 17, 2017
Priority date	Dec 19, 2011
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

First claim

What is claimed is:

1. A non-planar semiconductor device, comprising:
a semiconducting channel region comprising a three-dimensional body above a substrate, the substrate having a top surface;
a gate electrode stack surrounding at least a top surface and a pair of sidewalls of the three-dimensional body of the semiconductor channel region;
a pair of insulating sidewall spacers adjacent the gate electrode stack;
metallic source and drain regions disposed above the substrate, on either side of the semiconducting channel region, each of the metallic source and drain regions having a profile, wherein a portion of each of the metallic source and drain regions is vertically beneath the gate electrode stack along a direction normal to the top surface of the substrate;
a first semiconducting out-diffusion region disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region, wherein a portion of the first semiconducting out-diffusion region is disposed under one of the pair of insulating sidewall spacers and vertically beneath the gate electrode stack along the direction normal to the top surface of the substrate; and
a second semiconducting out-diffusion region disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region, wherein a portion of the second semiconducting out-diffusion region is disposed under another one of the pair of insulating sidewall spacers and vertically beneath the gate electrode stack along the direction normal to the top surface of the substrate, wherein the metallic source and drain regions have rounded profiles, and the first and second semiconducting out-diffusion regions are conformal with the rounded profiles.

2. The non-planar semiconductor device of claim 1 , wherein the metallic source and drain regions comprise a conductive material selected from the group consisting of a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide.

3. The non-planar semiconductor device of claim 1 , wherein the metallic source and drain regions uniaxially stress the semiconducting channel region.

4. The non-planar semiconductor device of claim 1 , wherein the semiconductor device is an N-type device, the semiconducting channel region comprises silicon, and the first and second semiconducting out-diffusion regions comprise dopant impurity atoms selected from the group consisting of phosphorous and arsenic.

5. The non-planar semiconductor device of claim 4 , wherein the metallic source and drain regions comprise a material selected from the group consisting of a metal carbide or a metal aluminide.

6. The non-planar semiconductor device of claim 1 , wherein the semiconductor device is a P-type device, the semiconducting channel region comprises silicon, and the first and second semiconducting out-diffusion regions comprise boron dopant impurity atoms.

7. The non-planar semiconductor device of claim 6 , wherein the metallic source and drain regions comprise a material selected from the group consisting of a metal nitride, a metal carbide, or a metal silicide.

8. The non-planar semiconductor device of claim 1 , wherein the substrate is a bulk substrate, and the three-dimensional body is continuous with the bulk substrate.

9. The non-planar semiconductor device of claim 1 , wherein the substrate includes an insulating layer, and the three-dimensional body is an isolated three-dimensional body.

Assignees

• Intel Corp

Inventors

• Giles Martin D
• Cappellani Annalisa
• Gardner Sanaz
• Rios Rafael
• Weber Cory E
• Budrevich Aaron A

Classifications

• H10P50/648

  Anisotropic liquid etching · CPC title

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title