CTE compensation for wafer-level and chip-scale packages and assemblies

Patent metadata

Field	Value
Publication number	US-10847469-B2
Application number	US-201715651531-A
Country	US
Kind code	B2
Filing date	Jul 17, 2017
Priority date	Apr 26, 2016
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween.

First claim

What is claimed is:

1. A microelectronic structure having CTE compensation for use in wafer-level and chip-scale packages, comprising:
a plurality of substrate tiles each having a generally planar upper surface, the upper surfaces of the tiles disposed within a common plane to provide a generally planar grid of the tiles, each respective pair of adjacent tiles having a gap disposed therebetween;
a spring structure spanning the gap and connecting the adjacent tiles, the spring structure configured to permit movement of the adjacent tiles relative to one another to provide compensation for thermal expansion or contraction of the tiles;
a respective opening extending through each substrate tile from the upper surface to an opposing lower surface;
an electrically conductive post extending through each opening from the upper surface to the lower surface; and
a device layer attached above the upper surfaces of the common plane, the device layer comprising a three-dimensional metal structure which includes a plurality of antenna radiators each disposed on a respective one of the conductive posts, with each antenna radiator suspended above the common plane.

2. The microelectronic structure of claim 1 , wherein the substrate tiles comprise a semiconductor material.

3. The microelectronic structure of claim 1 , wherein the substrate tiles comprise metal.

4. The microelectronic structure of claim 1 , wherein the spring structure comprises a membrane.

5. The microelectronic structure of claim 1 , wherein the spring structure comprises a 2-dimensional serpentine structure.

6. The microelectronic structure of claim 1 , wherein the spring structure comprises a metal.

7. The microelectronic structure of claim 1 , wherein the spring structure comprises a U-shaped membrane having a longitudinal axis that is disposed parallel to an edge of the upper surface of the selected tile to which the U-shaped membrane is attached.

8. The microelectronic structure of claim 1 , wherein the spring structure comprises a non-planar structure having a central region that extends upward above the common plane.

9. The microelectronic structure of claim 1 , wherein the spring structure is attached to the upper surfaces of the adjacent tiles.

10. The microelectronic structure of claim 1 , comprising a dielectric material disposed on the common plane and disposed within the gap.

11. The microelectronic structure of claim 1 , wherein the device layer comprises one or more of resistors, capacitors, and inductors.

12. The microelectronic structure of claim 1 , wherein the three-dimensional metal/dielectric structures include one or more of coaxial waveguides, Wilkinson combiner/dividers, Gysel combiner/dividers, and filters.

13. The microelectronic structure of claim 1 , wherein the device layer is attached to the upper surfaces with a dielectric material disposed therebetween.

14. The microelectronic structure of claim 1 , wherein the plurality of tiles each comprise multiple adjacent layers of metal disposed in direct contact to one another parallel to the upper surface.

15. The microelectronic structure of claim 1 , wherein the plurality of tiles is electrically continuous.

16. The microelectronic structure of claim 1 , comprising a semiconductor chip or wafer attached to the lower surface and electrically connected to the conductive posts to electrically connect the chip or wafer to the antenna radiators.

17. The microelectronic structure of claim 16 , wherein the wafer comprises one or more of ceramic substrate, a glass substrate, and a printed circuit board.

18. A method of forming a three-dimensional microstructure by a sequential build process, comprising:
disposing a plurality of layers over a substrate, wherein the layers comprise one or more layers of a conductive material and one or more layers of a sacrificial material, thereby forming a structure above the substrate, the structure comprising the microelectronic structure of claim.

19. The method of claim 18 , wherein the spring structure is formed of the conductive material.

20. The method of claim 18 , comprising removing the sacrificial material.

21. The method of claim 18 , comprising removing the substrate.

22. The method of claim 18 , wherein the spring structure comprises a membrane.

23. The method of claim 18 , wherein the spring structure comprises a 2-dimensional serpentine structure.

24. The method of claim 18 , wherein the spring structure comprises a U-shaped membrane having a longitudinal axis that is disposed parallel to an edge of the upper surface of the selected tile to which the u-shaped membrane is attached.

25. The method of claim 18 , wherein the spring structure comprises a non-planar structure having a central region that extends upward above the common plane.

26. The method of claim 18 , wherein the spring structure is attached to the upper surfaces of the adjacent tiles.

27. The method of claim 18 , wherein the step of disposing a plurality of layers over a substrate comprises disposing one or more layers of a dielectric material.

28. The method of claim 18 , wherein the substrate comprises one or more of ceramic substrate, a glass substrate, and a printed circuit board.

29. The method of claim 18 , wherein the device layer comprises one or more of resistors, capacitors, inductors, and the three-dimensional metal/dielectric structures.

30. The microelectronic structure of claim 29 , wherein the three-dimensional metal/dielectric structures include one or more of coaxial waveguides, antennas, Wilkinson combiner/dividers, Gysel combiner/dividers, and filters.

31. The method of claim 18 , wherein the tiles each comprise a lower surface opposing the upper surface and comprising electrically connecting a semiconductor chip or wafer to the lower surface.

32. The microelectronic structure of claim 1 , wherein the spring structure includes a sheet of material that extends across, and is flush with, the upper surfaces of the plurality of substrate tiles.

33. The microelectronic structure of claim 1 , wherein the spring structure includes a membrane of metal disposed conformally over the upper surfaces of the plurality of substrate tiles to provide a flexible three-dimensional membrane spring.

34. The microelectronic structure of claim 1 , comprising a sacrificial material disposed in the gaps between each pair of adjacent tiles, the sacrificial material extending upward above the uppers surfaces of the tiles to provide a spring support, wherein the spring structure is conformally disposed over the spring support.

35. The microelectronic structure of claim 34 , wherein the sacrificial material comprises photoresist.

36. The microelectronic structure of claim 1 , comprising a radiator gap between adjacent antenna radiators and wherein the radiator gap is disposed above, and in registration with, the gap between adjacent tiles.

37. The microelectronic structure of claim 1 , comprising a radiator gap between adjacent antenna radiators and wherein the radiator gap is disposed above, and in registration with, the spring structure.

Assignees

• Nuvotronics Inc
• Cubic Corp

Inventors

• Vanhille Kenneth J
• Caba Aaron C
• Beroz Masud
• Jordan Jared W
• Smith Timothy A
• Boryssenko Anatoliy O
• Huettner Steven E

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• H10W72/07554

  changes in dispositions · CPC title