Interconnect assemblies with through-silicon vias and stress-relief features

Patent metadata

Field	Value
Publication number	US-10847442-B2
Application number	US-201414188367-A
Country	US
Kind code	B2
Filing date	Feb 24, 2014
Priority date	Feb 24, 2014
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate structure having a first side, a second side, and a thickness, wherein the substrate structure includes circuitry at the first side and a semiconductor substrate; and
a conductive interconnect extending through at least a portion of the substrate structure, the conductive interconnect including—
a through-silicon via extending from the first side toward the second side and including a conductive core and a spacer material, wherein the spacer material is conductive and different from conductive material of the conductive core,
a stress-relief feature is a closed empty chamber positioned within the conductive core and has sides defined by exposed surfaces of the conductive core, wherein a first end of the stress-relief feature is proximate to and closer to the first side of the substrate structure than a bottom of the substrate,

wherein at least a portion of the spacer material extends across and defines a second end of the stress-relief feature and is positioned directly between the second end and the second side of the substrate,
wherein an outermost side portion of the conductive core is positioned radially outward, relative to a via axis of the through-silicon via, of the stress-relief feature and is positioned directly between the stress-relief feature and the circuitry, and
wherein the stress-relief feature has a depth, relative to the first side of the substrate, greater than twice a thickness of the circuitry such that the stress-relief feature accommodates (a) thermal expansion and/or thermal contraction of the outermost side portion of the conductive material and (b) thermal expansion and/or thermal contraction of the circuitry, wherein the depth is less than the thickness of the substrate.

2. The semiconductor device of claim 1 wherein the semiconductor substrate has a first coefficient of thermal expansion, wherein the conductive material of the through-silicon via has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion, and wherein the stress-relief feature is a gap configured to be:
(a) narrowed by thermal expansion of the through-silicon via; and/or
(b) widened by thermal contraction of the through-silicon via.

3. The semiconductor device of claim 1 , further including a liner material between the through-silicon via and the substrate structure, wherein the through-silicon via includes the conductive core.

4. The semiconductor device of claim 1 wherein a portion of the through-silicon via is positioned between the stress-relief feature and the second side of the substrate structure.

5. The semiconductor device of claim 1 wherein the depth of the stress-relief feature in a direction parallel to the via axis is less than a longitudinal length of the through-silicon via.

6. The semiconductor device of claim 1 wherein the stress-relief feature has a width equal to or greater than a distance of thermal expansion of the conductive material caused by a temperature increase of about 200 Celsius.

7. The semiconductor device of claim 1 wherein the stress-relief feature is dimensioned to accommodate thermal expansion and/or thermal contraction of the through-silicon via to inhibit fracturing of material of the substrate structure surrounding the through-silicon via when a temperature of the through-silicon via is increased from room temperature to about 200 Celsius.

8. The semiconductor device of claim 1 wherein the conductive interconnect is a first conductive interconnect and the stress-relief feature is a first stress-relief feature, and the semiconductor device further includes
a second conductive interconnect that includes a second stress-relief feature, wherein the first stress-relief feature and the second stress-relief feature cooperate to inhibit thermal stresses in the substrate structure caused by thermal expansion and/or thermal contraction of the first and second conductor interconnects to prevent forming a crack that extends from the first conductive interconnect to the second conductive interconnect.

9. The semiconductor device of claim 1 wherein the stress-relief feature is a U-shaped annular recess with an axis of symmetry substantially aligned with the longitudinal axis of the through-silicon via.

10. The semiconductor device of claim 1 , wherein the stress-relief feature is an etched gap.

11. A semiconductor assembly, comprising:
a substrate structure having a first side and a second side and comprising semiconductor material and circuitry at the first side;
a first conductive interconnect extending through a first portion of the substrate structure and including—
a first through-silicon via extending from the first side toward the second side and comprising a conductive material and a spacer material different from the conductive material, and
a first stress-relief feature positioned within the conductive material to accommodate thermal expansion and/or thermal contraction of an outer portion of the conductive material that causes stress in the substrate structure, the outer portion is located directly between the circuitry and the first stress-relief feature and is laterally adjacent to a dielectric material between the first through-silicon via and the substrate structure, a surface of the outer portion defines a side of the first stress-relief feature having a first depth that is (a) less than half of a longitudinal length of the first through-silicon via and (b) at least twice a thickness of the circuitry, wherein at least a portion of the spacer material is positioned directly between the stress-relief feature and the second side and extends across most of a width of an empty chamber of the stress-relief feature; and

a second conductive interconnect extending through a second portion of the substrate structure and being spaced apart from the first conductive interconnect, the second conductive interconnect including—
a second through-silicon via extending from the first side toward the second side, and
a second stress-relief feature positioned within conductive material of the second through-silicon via to accommodate thermal expansion and/or thermal contraction of the second through-silicon via and having a second depth that is less than half of a longitudinal length of the second through-silicon via.

12. The semiconductor assembly of claim 11 wherein the substrate structure has a first surface facing the first conductive interconnect and a second surface facing the second conductive interconnect, wherein the first stress-relief feature and the second stress-relief feature are configured to accommodate thermal expansion and/or thermal contraction of the first and second through-silicon vias, respectively, to prevent forming a crack that extends between the first and second surfaces of the substrate structure.

13. The semiconductor assembly of claim 11 wherein the first stress-relief feature is an annular gap.

14. A method of manufacturing a semiconductor device, the method comprising:
forming a conductive interconnect extending from a first side of a substrate structure toward a second side of the substrate structure; and
removing a spacer material located between a conductive core of the conductive interconnect and circuitry of the substrate structure to form a stress-relief feature of the conductive interconnect, wherein the spacer material is conductive and different from conductive material of the conductive core, wherein the stress-relief feature is an empty gap positioned within the conductive interconnect to compensate for thermal expansion and/or ther

Assignees

• Micron Technology Inc

Inventors

• Li Hongqi
• Jindal Anurag
• Lu Jin
• Damarla Gowrisankar
• Ramalingam Shyam

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title