Memory system utilizing heterogeneous magnetic tunnel junction types in a single chip

Patent metadata

Field	Value
Publication number	US-10847198-B2
Application number	US-201816178105-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Nov 1, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A magnetic data recording system utilizing different magnetic memory element types to optimize competing performance parameters in a common memory chip. The memory system includes a first memory portion which can be a main memory and which includes magnetic memory elements of a first type, and a second memory region which can be a temporary memory region and which includes magnetic memory elements of a second type. A memory controller can be provided for controlling the input and retrieval of data to and from the first and second memory elements. The second, memory region can be a scratchpad memory or could also be cache type memory. The first type of magnetic memory elements can be designed for high data retention, whereas the second type of magnetic memory elements can be designed for fast write speed (low latency) and low write power consumption.

First claim

What is claimed is:

1. A magnetic memory system, comprising:
a magnetic memory array having a first portion and a second portion, the first portion including a first type of magnetic memory elements and the second portion including a second type of magnetic memory elements; and
a memory controller configured to allocate data to the first and second portions of the memory array;
wherein the first type of magnetic memory elements comprise a first type of magnetic tunnel junction and the second type of magnetic memory elements comprise a second type of magnetic tunnel junction element; and
wherein each of the first and second type of magnetic tunnel junctions has a free layer, and wherein the structure of the magnetic free layer of the first magnetic type of tunnel junction is different from the structure of the free layer of the second type of magnetic tunnel junction by one or more of the following:
thickness; insertion; magnetic composition and boron content.

2. The magnetic memory system as in claim 1 , wherein the first type of memory elements is configured to have a higher data retention than the second type of memory elements.

3. The magnetic memory system as in claim 1 , wherein the second type of memory elements is configured to have a lower latency than the first type of memory elements.

4. The magnetic memory system as in claim 1 , wherein the second type of magnetic memory elements is configured to have a lower write power than the first type of memory elements.

5. The magnetic memory system as in claim 1 , wherein the memory controller includes logic for writing data to the second portion of the memory array and software or built-in hardware logics for flushing the data from the second portion of the memory array to the first portion of the memory array.

6. The magnetic memory system as in claim 1 , wherein the second portion of the memory array is configured as scratch pad memory.

7. The magnetic memory system as in claim 1 , wherein the second portion of the memory array is configured as cache memory.

8. The magnetic memory system as in claim 1 , wherein the memory controller includes logic for moving data between the first portion of the memory array and the second portion of the memory array.

9. The magnetic memory system as in claim 1 , where in the first and second types of magnetic tunnel junction elements can have an in-plane magnetization or a perpendicular to plane magnetization.

10. The magnetic memory system as in claim 1 , wherein each of the first and second type of magnetic tunnel junctions have a non-magnetic barrier layer, and wherein the non-magnetic barrier layer of the first type of magnetic tunnel junction is different than the structure of the non-magnetic barrier layer of the second type of magnetic tunnel junction.

11. The magnetic memory system as in claim 1 , wherein each of the first and second types of magnetic tunnel junctions has a magnetic reference layer that is part of a synthetic antiferromagnetic structure, and wherein the synthetic antiferromagnetic structure of the first type of magnetic tunnel junction is different from the synthetic antiferromagnetic structure of the second type of magnetic tunnel junction, resulting in different characteristics including one or more of: magnetic offset field and magnetic stability.

12. The magnetic memory system as in claim 1 , wherein the first type of magnetic tunnel junction has a magnetic anisotropy that is different from a magnetic anisotropy of the second type of magnetic tunnel junction.

13. The magnetic memory system as in claim 1 , wherein the first type of magnetic tunnel junction has a size that is different from a size of the second type of magnetic tunnel junction.

14. A magnetic memory system, comprising:
a first array magnetic memory elements of a first type;
a second array of magnetic memory elements of a second type; and
a memory controller for controlling input and retrieval of data to and from the first and second arrays of magnetic memory elements; wherein
the memory elements of the first type have a higher data retention than the memory elements of the second type, and the memory elements of the second type have a lower latency than the memory elements of the first type;
wherein the memory controller is functional to:
control the input and retrieval of data to and from the second array of memory elements;
control the input and retrieval of data to and from the first array of memory elements; and

control the input and retrieval of data between the second array of memory elements and the first array of memory elements;
wherein the first type of magnetic memory elements comprise a first type of magnetic tunnel junction and the second type of magnetic memory elements comprise a second type of magnetic tunnel junction element; and
wherein each of the first and second type of magnetic tunnel junctions has a free layer, and wherein the structure of the magnetic free layer of the first magnetic type of tunnel junction is different from the structure of the free layer of the second type of magnetic tunnel junction by one or more of the following: thickness; insertion; magnetic composition and boron content.

15. The magnetic memory system as in claim 14 , wherein the magnetic memory elements of the first type have a higher thermal stability than the memory elements of the second type.

16. The magnetic memory system as in claim 14 , wherein the magnetic memory elements of the second type have a lower write power then the magnetic memory elements of the first type.

17. The magnetic memory system as in claim 14 , wherein the first and second arrays of memory elements are located on a common chip.

18. The magnetic memory system as in claim 14 , wherein the second array of memory elements is configured as scratchpad memory.

19. The magnetic memory system as in claim 14 , wherein the second array of memory elements is a cache memory.

20. The magnetic memory system as in claim 14 , wherein the memory controller is operable to record data to the second array of memory elements and also to flush data from the second array of memory elements to the first array of memory elements.

21. The magnetic memory system as in claim 14 , wherein the memory controller is operable to:
record data to the second array of memory elements;
flush data from the second array of memory elements to the first array of memory elements; and
retrieve data from the first array of memory elements.

22. The magnetic memory system as in claim 21 , wherein the second array of memory elements is a scratchpad memory.

23. The magnetic memory system as in claim 14 , wherein the memory controller includes computer readable instructions for:
controlling the input and retrieval of data to and from the second array of memory elements;
controlling the input and retrieval of data to and from the first array of memory elements; and
controlling the input and retrieval of data between the second array of memory elements and the first array of memory elements.

Assignees

• Spin Memory Inc

Inventors

• Bozdag Kadriye Deniz
• Ryan Eric Michael
• Kim Kuk-Hwan

Classifications

• G11C11/1659

  Cell access · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• H01L27/222

  Electricity · mapped topic