Power transistor driver with reduced spikes for switching converters

Patent metadata

Field	Value
Publication number	US-10840795-B1
Application number	US-201916655080-A
Country	US
Kind code	B1
Filing date	Oct 16, 2019
Priority date	Oct 16, 2019
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A driver for driving a power transistor, the driver having: a first transistor, and a second transistor; wherein (1) when the first transistor is turned on, the second transistor is simultaneously turned on, and wherein after the second transistor remains on for a first time period, the second transistor is turned off for a second time period during when a switching voltage at a second terminal of the power transistor is rising, and the second transistor is turned on after the second time period is over; and (2) when the first transistor is turned off, the second transistor is simultaneously turned off.

First claim

I claim:

1. A driver for driving a power transistor having a control terminal, a first terminal and a second terminal, the driver comprising:
a first transistor, having a control terminal configured to receive a first driving signal, a first terminal coupled to a power source, a second terminal coupled to the control terminal of the power transistor; and
a second transistor, having a control terminal configured to receive a second driving signal, a first terminal coupled to the power source, and a second terminal coupled to the control terminal of the power transistor; wherein
(1) when the first transistor is turned on, the second transistor is simultaneously turned on, and wherein after the second transistor remains on for a first time period, the second transistor is turned off for a second time period during when a switching voltage at the second terminal of the power transistor is rising, and the second transistor is turned on after the second time period is over; and
(2) when the first transistor is turned off, the second transistor is simultaneously turned off; wherein
the second time period begins in response to a power control signal at the control terminal of the power transistor reaching a first power control signal threshold, and ends in response to the power control signal reaching a second power control signal threshold, and wherein the first power control signal threshold is higher than a turn on threshold of the power transistor, and the second power control signal threshold is higher than the first power control signal
further comprising a driving control signal generating circuit wherein the driving control signal generating circuit comprises:
a first threshold circuit, having a first input terminal configured to receive the switching voltage, a second input terminal configured to receive a first switching voltage threshold, and an output terminal configured to provide a first threshold detecting signal based on the switching voltage and the first switching voltage threshold;
a second threshold circuit, having a first input terminal configured to receive the switching voltage, a second input terminal configured to receive a second switching voltage threshold, and an output terminal configured to provide a second threshold detecting signal based on the switching voltage and the second switching voltage threshold; and
a logic circuit, having a first input terminal configured to receive the first threshold detecting signal, a second input terminal configured to receive the second threshold detecting signal, a third input terminal configured to receive a switching control signal, a first output terminal and a second output terminal configured to provide a first driving control signal and a second driving control signal respectively, wherein the first driving control signal is generated based on performing a logic operation to the switching control signal, and the second driving control signal is generated based on performing a logic operation to the first threshold detecting signal, the second threshold detecting signal and the switching control signal, wherein:
the first threshold circuit comprises a first comparator; and
the second threshold circuit comprises a second comparator.

2. The driver of claim 1 , wherein the logic circuit further comprises:
a first RS latch, having a set terminal configured to receive the first threshold detecting signal, a reset terminal configured to receive the switching control signal, and a non-inverting output terminal configured to provide a first latch output signal;
a second RS latch, having a set terminal configured to receive the second threshold detecting signal, a reset terminal configured to receive the switching control signal, and an inverting output terminal configured to provide a second latch output signal; and
a logic gate circuit, having a first input terminal configured to receive the first latch output signal, a second input terminal configured to receive the second latch output signal, a third input terminal configured to receive the switching control signal, a first output terminal and a second output terminal configured to provide a first driving control signal and a second driving control signal respectively, wherein the first driving control signal is generated based on performing a logic operation to the switching control signal, and the second driving control signal is generated based on performing a logic operation to the first latch output signal, the second latch output signal and the switching control signal.

3. The driver of claim 1 , further comprising a driving control signal generating circuit, wherein the driving control signal generating circuit comprises:
a first threshold circuit, having an input terminal configured to receive a power control signal, an output terminal configured to provide a first threshold detecting signal;
a second threshold circuit, having an input terminal configured to receive the power control signal, and an output terminal configured to provide a second threshold detecting signal; and
a logic circuit, having a first input terminal configured to receive the first threshold detecting signal, a second input terminal configured to receive the second threshold detecting signal, a third input terminal configured to receive a switching control signal, a first output terminal and a second output terminal configured to provide a first driving control signal and a second driving control signal respectively, wherein the first driving control signal is generated based on performing a logic operation to the switching control signal, and the second driving control signal is generated based on performing a logic operation to the first threshold detecting signal, the second threshold detecting signal and the switching control signal.

4. The driver of claim 3 , wherein the first threshold circuit comprises:
a current source, configured to provide a current; and
a MOSFET, configured to receive the current provided by the current source, wherein the MOSFET has a control terminal configured to receive the power control signal.

5. The driver of claim 3 , wherein the second threshold circuit further comprises one inverter or a plurality of inverters, and wherein when the second threshold circuit comprises the plurality of inverters, the plurality of inverters are coupled in a way that an output of a pre-stage inverter is coupled to an input of an adjacent post-stage inverter.

6. The driver of claim 3 , wherein:
the first threshold circuit having a first comparator configured to receive the power control signal and a first power control threshold signal, and to provide the first threshold detecting signal based on a comparison result of the power control signal and the first power control threshold signal; and
the first threshold circuit having a second comparator configured to receive the power control signal and a second power control threshold signal, and to provide the second threshold detecting signal based on a comparison result of the power control signal and the second power control threshold signal.

7. The driver of claim 1 , further comprising a driving control signal generating circuit, wherein the driving control signal generating circuit comprises:
a delay circuit, having an input terminal configured to receive a switching control signal, and an output terminal configured to provide a delay signal, wherein a time delay between the switching control signal and the delay signal equals to the first time period;
a second threshold circuit, having an input terminal configured to receive the power control signal, and an output terminal configured to provide a second threshold detecting signal; and
a logic circuit, having a first input terminal configured to receive th

Assignees

• Monolithic Power Systems Inc

Inventors

• Nguyen James

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M1/0029

  Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title