Ultra high voltage semiconductor device with electrostatic discharge capabilities

Patent metadata

Field	Value
Publication number	US-10840371-B2
Application number	US-201916663654-A
Country	US
Kind code	B2
Filing date	Oct 25, 2019
Priority date	Feb 14, 2014
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device comprising:
providing a first layer over a semiconductor substrate;
forming a drain region in the first layer, wherein the forming the drain region comprises:
performing a first implanting process to form an initial drain region with a first concentration of dopants and extending from a first surface to a first depth in the first layer, the first implanting process forming the initial drain region having a rectangular well portion interposing and a first drain end portion and a second drain end portion, each of the first drain end portion and the second drain end portion having an interface with and end of the rectangular well portion, the interface extending downward from the first surface; and
performing a second implanting process to form the rectangular well portion having a second concentration of the dopants within the initial drain region, wherein the second concentration is greater than the first concentration and wherein the first drain end portion and the second drain end portion of the initial drain region are maintained at the first concentration including the first surface, the first depth, and the interfaces with the rectangular well portion during the second implanting process; and

forming a source region spaced a distance from and surrounding the drain region in the first layer.

2. The method of claim 1 , wherein the first implanting process includes introducing n-type dopants to form the initial drain region, and wherein the second implanting process includes introducing n-type dopants to form the rectangular well portion of the second concentration of N+.

3. The method of claim 2 , wherein the forming the source region includes implanting p-type dopants.

4. The method of claim 1 , wherein the first implanting process defines circular edges for the first drain end portion and the second drain end portion.

5. The method of claim 1 , further comprising: forming a gate electrode over the source region.

6. The method of claim 1 , further comprising: forming an oxide region between the drain region and the source region.

7. A method comprising:
growing a first layer over a semiconductor substrate;
forming a drain region in the first layer wherein the drain region has a length extending from a first terminal point to a second terminal point and a width, the length being greater than the width, wherein the drain region has a first circular end region including the first terminal point and a second circular end region including the second terminal point, the first and second circular end regions having a first concentration of a second dopant type and a rectangular intermediate portion extending between the first and second circular end regions having a second concentration of the second dopant type, greater than the first concentration;
forming a source region of a first dopant type at a first concentration in the first layer, wherein the source region is spaced a distance from and surrounding the drain region in the first layer;
implanting the first dopant type to form a first well of a second concentration in the source region, wherein the second concentration is greater than the first;
implanting a second dopant type to form a second well in the source region, wherein the second dopant type is different than the first dopant type; and
forming a gate electrode over the first layer.

8. The method of claim 7 , further comprising:
wherein the forming the gate electrode forms the gate electrode over the source region.

9. The method of claim 7 , further comprising:
forming a dielectric layer between the source region and the drain region.

10. The method of claim 9 , wherein the gate electrode is formed at least partially over the dielectric layer.

11. The method of claim 9 , wherein the forming the dielectric layer includes forming a trench between the source region and the drain region, wherein the dielectric layer is formed in the trench.

12. The method of claim 7 , wherein a portion of the drain region is formed at a same time as implanting the second dopant type to form the second well in the source region.

13. The method of claim 7 , wherein the forming the drain region includes providing the second dopant type.

14. The method of claim 7 , wherein the forming the drain region in the first layer includes:
performing a first implant to form an area with a first concentration of a second dopant type; and
performing a second implant to form a rectangular well portion of a second concentration of the second dopant type within the area, wherein the second concentration is greater than the first concentration wherein a first drain end portion and a second drain end portion are maintained at the first concentration during the implanting of the second concentration.

15. The method of claim 14 , wherein the second dopant type is n-type dopants.

16. A method comprising:
forming a drain region of a first dopant type having a rectangular portion, a first drain end portion, and a second drain end portion;
forming a source region of a second dopant type, wherein the source region is spaced a distance from and surrounding the drain region;
wherein the forming the source region includes:
forming the source region having the second dopant type;
forming a first well of an increased concentration of the second dopant type in the source region; and
implanting the first dopant type to form a second well within the source region;

forming a gate electrode over the source region;
forming a first oxide layer between the drain region and the source region; and
forming a second oxide layer interfacing an edge of the first well of the increased concentration.

17. The method of claim 16 , wherein the forming the first oxide layer and the forming the second oxide layer include oxidation to form a respective field oxide (FOX) region.

18. The method of claim 16 , wherein the first oxide layer extends from an edge of the drain region and an edge of the source region.

19. The method of claim 16 , wherein the forming the drain region including forming the rectangular portion of a first concentration of the first dopant type and the first drain end portion and the second drain end portion have a second concentration of the first dopant type, the second concentration is less than the first concentration.

20. The method of claim 16 , wherein implanting the first dopant type to form the second well within the source region is performed at a same time as implanting the rectangular portion of the drain region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tsai-Feng
• Shen Chih-Heng
• Yang Chun-Yi
• Huang Kun-Ming
• Chu Po-Tao
• Wang Shen-Ping

Classifications

• H10D89/811

  using FETs as protective elements · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title