Shielding in a unit capacitor array

Patent metadata

Field	Value
Publication number	US-10840232-B2
Application number	US-201816019746-A
Country	US
Kind code	B2
Filing date	Jun 27, 2018
Priority date	Jun 27, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.

First claim

What is claimed is:

1. An array of capacitors on an integrated circuit comprising:
a plurality of unit capacitors, each of the unit capacitors including,
an isolated capacitor node formed in a vertical structure on two or more metal layers of the integrated circuit and coupled by at least one via between each metal layer;
a shared capacitor node, the shared capacitor node formed adjacent to the isolated capacitor node, the shared capacitor node coupled through a low impedance path to a common node to which other shared capacitor nodes of the plurality of unit capacitors are coupled;
a shield node formed adjacent to the isolated capacitor node in at least one metal layer in which the isolated capacitor node is formed;
wherein each isolated capacitor node of the plurality of unit capacitors is driven by a different one of a plurality of separate control lines; and
wherein each shield node of the plurality of unit capacitors is coupled to a ground node.

2. The array of capacitors as recited in claim 1 wherein:
the shared capacitor node is disposed in an Nth metal layer above an N−1 metal layer in which a top the isolated capacitor node is disposed, where N is an integer greater than or equal to 3.

3. The array of capacitors as recited in claim 1 wherein:
the shared capacitor node includes two fingers in a same metal layer in which a top of the isolated capacitor node is disposed, the top of the isolated capacitor node being disposed between the two fingers of the shared capacitor node in the same metal layer.

4. The array of capacitors as recited in claim 1 wherein the shared capacitor node forms a ring around the isolated capacitor node in a same metal layer in which a top of the isolated capacitor node is disposed.

5. The array of capacitors as recited in claim 1 wherein the shield node forms a ring around the isolated capacitor node and is disposed in a different metal layer than the shared capacitor node.

6. The array of capacitors as recited in claim 1 wherein a conductor is electrically connected to a base of the isolated capacitor node and the conductor terminates underneath the shield node and wherein the conductor is one of the separate control lines.

7. The array of capacitors as recited in claim 1 wherein routing of conductors into the array to connect to respective isolated capacitor nodes is disposed in a single metal layer.

8. The array of capacitors as recited in claim 7 wherein respective ones of the conductors enter the array on each of four sides of the array in the single metal layer.

9. The array of capacitors as recited in claim 7 wherein the shield node is formed in a metal layer closer to the single metal layer than to an Nth metal layer in which the shared capacitor node is disposed, where N is an integer of at least 4.

10. The array of capacitors as recited in claim 1 wherein the array is a binary weighted capacitor array having common centroid placements for at least higher weighted capacitor values to thereby cancel linear process gradients in x and y directions for the higher weighted capacitor values.

11. The array of capacitors as recited in claim 1 further comprising a plurality of dummy unit capacitors formed on a periphery of the array, the dummy unit capacitors coupled to the ground node.

12. A method of making a capacitor array comprising:
forming a plurality of unit capacitors, wherein forming each of the unit capacitors includes,
forming an isolated capacitor node in a vertical structure including two or more metal layers of an integrated circuit and one or more vias between each of the two or more metal layers;
forming a shared capacitor node adjacent to a first portion of the isolated capacitor node in an Nth metal layer, N being an integer of three or more;
forming a low impedance path to couple the shared capacitor node to a common node to which other shared capacitor nodes of the plurality of unit capacitors are coupled;
forming a shield node in at least one metal layer other than the Nth metal layer; and
forming a shield conductor to couple the shield node to a ground node.

13. The method of making the capacitor array as recited in claim 12 further comprising:
forming a top of the isolated capacitor node in an Nth−1 metal layer.

14. The method of making the capacitor array as recited in claim 12 further comprising forming the shared capacitor node as two fingers in a same metal layer in which a top of the isolated capacitor node is disposed, the top of the isolated capacitor node being disposed between the two fingers in the same metal layer.

15. The method of making the capacitor array as recited in claim 12 further comprising forming the shared capacitor node as a ring structure around the isolated capacitor node in a same metal layer in which a top of the isolated capacitor node is formed.

16. The method of making the capacitor array as recited in claim 12 further comprising forming the shield node in a ring around the isolated capacitor node in a different metal layer than the Nth metal layer.

17. The method of making the capacitor array as recited in claim 12 further comprising:
using a single metal layer to route conductors into the capacitor array to couple to respective isolated capacitor nodes, the conductors being respective control signals; and
terminating the conductors that connect to the respective isolated capacitor nodes underneath respective shield nodes.

18. The method of making the capacitor array as recited in claim 17 further comprising forming the conductors to enter the capacitor array on each of four sides of the capacitor array in the single metal layer.

19. The method of making the capacitor array as recited in claim 17 further comprising forming the shield node in a metal layer closer to the single metal layer than to the Nth metal layer in which the shared capacitor node is disposed, where N is an integer of four or more.

20. The method of making a capacitor array as recited in claim 12 further comprising aggregating unit capacitors in the capacitor array to form a binary weighted capacitor array having common centroid placements for higher weighted aggregated capacitor values to thereby cancel linear process gradients in x and y directions for the higher weighted aggregated capacitor values.

21. The method as recited in claim 12 further comprising:
forming conductors to couple to respective isolated capacitor nodes of the plurality of unit capacitors as respective control signals; and
terminating the conductors that connect to the respective isolated capacitor nodes underneath respective shield nodes.

22. An array of capacitors comprising:
a plurality of unit capacitors, each unit capacitor including,
an isolated capacitor node formed on multiple metal layers of an integrated circuit with at least one via between each of the multiple metal layers;
a shared capacitor node adjacent to the isolated capacitor node in at least one of a vertical or horizontal direction;
a shield node formed adjacent to the isolated capacitor node on at least one of the multiple metal layers and on a different metal layer than the shared capacitor node; and
wherein the shield node is coupled to a ground node and is interposed between a control line connected to a base of the isolated capacitor node and the shared capacitor node.

23. The array of capacitors as recited in claim 22 wherein the control line terminates underneath the shield node.

Assignees

• Silicon Lab Inc

Inventors

• Caffee Aaron J
• Drost Brian G

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W20/423

  Shielding layers · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/714

  having horizontal extensions · CPC title