Precision half cell for sub-FEMTO unit cap and capacitive DAC architecture in SAR ADC

Patent metadata

Field	Value
Publication number	US-9418788-B2
Application number	US-201514643478-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Mar 16, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.

First claim

What is claimed is:

1. A capacitive device, comprising:
a first conductor formed on a lower metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to a first terminal;
a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and
a plurality of parallel wires partitioned into a plurality of layers, wherein parallel wires included in each layer of the plurality of layers are formed in a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers excludes the upper metal wiring layer and the lower metal wiring layer,
wherein:
a first parallel wire and a second parallel wire of each layer of the plurality of layers is coupled to a second terminal;
a third parallel wire of each layer of the plurality of layers is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;
a fourth parallel wire of each layer of the plurality of layers is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;
a fifth parallel wire of each layer of a first subset of the plurality of layers is coupled to the second conductor, and wherein the fifth parallel wire of each layer of a second subset of the plurality of layers is coupled to the first conductor; and
the fifth parallel wire of each layer of the plurality of layers is adjacent to the first parallel wire and the second parallel wire.

2. The capacitive device of claim 1 , wherein the first subset of the plurality of layers is mutually exclusive to the second subset of the plurality of layers.

3. The capacitive device of claim 2 , wherein a number of layers included in the first subset of the plurality of layers is equal to a number of layers included in the second subset of the plurality of layers.

4. The capacitive device of claim 1 , wherein an edge of the third parallel wire included in a given layer of the plurality of layers is parallel to an edge of the third parallel wire included in any other given layer of the plurality of layers.

5. The capacitive device of claim 1 , wherein a dielectric material is included between each adjacent parallel wire in a given layer of the plurality of layers.

6. The capacitive device of claim 1 , wherein the second conductor is coupled to a third terminal.

7. The capacitive device of claim 6 , wherein the third terminal is coupled to a ground voltage reference.

8. A method comprising:
receiving an input signal;
coupling the input signal to a first terminal of a capacitive device, wherein the capacitive device includes:
a first conductor formed on a lower metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to the first terminal;
a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and
a plurality of parallel wires partitioned into a plurality of layers, wherein parallel wires included in each layer of the plurality of layers are formed on a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers is between the upper metal wiring layer and the lower metal wiring layer,
wherein:
a first parallel wire and a second parallel wire of each layer of the plurality of layers is coupled to a second terminal;
a third parallel wire of each layer of the plurality of layers is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;
a fourth parallel wire of each layer of the plurality of layers is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;
a fifth parallel wire of each layer of a first subset of the plurality layers is coupled to the second conductor, and wherein the fifth parallel wire of each layer of a second subset of the plurality of layers is coupled to the first conductor;
the fifth parallel wire of each layer of the plurality of layers is adjacent to the first parallel wire and the second parallel wire; and

coupling an output signal at the second terminal, wherein the output signal is dependent upon a voltage level across the capacitive device; and
coupling the first terminal to a reference voltage dependent upon a determination that the voltage level across the capacitive device is the same as a voltage level of the input signal.

9. The method of claim 8 , further comprising setting a value of a data bit to one in response to a determination that the voltage level across the capacitive device is greater than a voltage level of the reference voltage.

10. The method of claim 8 , further comprising determining a value corresponding to the voltage level of the input signal.

11. The method of claim 8 , wherein the first subset of the plurality of layers is mutually exclusive to the second subset of the plurality of layers and wherein a number of layers included in the first subset of the plurality of layers is equal to a number of layers included in the second subset of the plurality of layers.

12. The method of claim 8 , wherein an edge of the third parallel wire included in a given layer of the plurality of layers is aligned to an edge of the third parallel wire included in any other given layer of the plurality of layers.

13. The method of claim 8 , wherein the second conductor is coupled to a third terminal, and wherein the third terminal is coupled to a ground signal.

14. A system comprising:
a plurality of capacitors, wherein at least one capacitor of the plurality of capacitors includes:
a first conductor formed on a lower metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to a first terminal;
a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and
a plurality of parallel wires partitioned into a plurality of layers, wherein parallel wires included in each layer of the plurality of layers are formed on a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers is between the upper metal wiring layer and the lower metal wiring layer,
wherein:
a first parallel wire and a second parallel wire of each layer of the plurality of layers is coupled to a second terminal;
a third parallel wire of each layer of the plurality of layers is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;
a fourth parallel wire of each layer of the plurality of layers is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;
a fifth parallel wire of each layer of a first subset of the plurality layers is coupled to the second conductor, and wherein the fifth parallel wire of each layer of a second subset of the plurality of layers is coupled to the first conductor; and
the fifth parallel wire of each layer of the plurality of layers is adjacent to the first parallel wire and the second parallel wire;

a control circuit coupled to the first terminal of each capacitor of the plurality of capacitors, wherein the control circuit is configured to switch a coupling of the first terminal of a given capacitor of the plurality of capacitors from an input voltage signal to a reference voltage signal in response to a determination that a voltage level across the given capacitor is the same as a voltage level of the input voltage signal; and
a comparator coupled to the second terminal of each capacitor

Assignees

• Apple Inc

Inventors

• Srinivas Vijay
• Keramat Mansour
• Chao Yuan-Ju

Classifications

• H01G4/01 Primary

  Form of self-supporting electrodes · CPC title

• H01G4/38

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• H01G4/129

  containing a glassy phase, e.g. glass ceramic · CPC title

• H01G4/228

  Terminals · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title