Under-bump-metallization structure and redistribution layer design for integrated fan-out package with integrated passive device

Patent metadata

Field	Value
Publication number	US-10840227-B2
Application number	US-201816129479-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	Nov 2, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

First claim

What is claimed is:

1. A semiconductor package comprising:
an integrated passive device (IPD) comprising:
one or more passive devices over a first substrate;
metallization layers over and electrically coupled to the one or more passive devices, wherein a topmost metallization layer of the metallization layers comprises:
a first plurality of conductive patterns; and
a second plurality of conductive patterns interleaved with the first plurality of conductive patterns; and

a first under bump metallization (UBM) structure over the topmost metallization layer, wherein the topmost metallization layer is between the first substrate and the first UBM structure, wherein the first UBM structure comprises:
a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and
a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

2. The semiconductor package of claim 1 , wherein the first plurality of conductive strips are configured to be electrically coupled to a power supply, and the second plurality of conductive strips are configured to be electrically coupled to a reference voltage.

3. The semiconductor package of claim 1 , wherein the first plurality of conductive patterns is parallel with the first plurality of conductive strips.

4. The semiconductor package of claim 3 , wherein the first UBM structure of the IPD further comprises:
a first conductive strip perpendicular to the first plurality of conductive strips, the first conductive strip being in a same plane with the first plurality of conductive strips, the first conductive strip physically connected to the first plurality of conductive strips; and
a second conductive strip perpendicular to the second plurality of conductive strips, the second conductive strip being in a same plane with the second plurality of conductive strips, the second conductive strip physically connected to the second plurality of conductive strips.

5. The semiconductor package of claim 1 , wherein the first plurality of conductive patterns is perpendicular to the first plurality of conductive strips.

6. The semiconductor package of claim 5 , wherein the first UBM structure of the IPD further comprises:
a first conductive strip perpendicular to the first plurality of conductive strips, the first conductive strip being in a same plane with the first plurality of conductive strips, the first conductive strip physically connected to the first plurality of conductive strips; and
a second conductive strip perpendicular to the second plurality of conductive strips, the second conductive strip being in a same plane with the second plurality of conductive strips, the second conductive strip physically connected to the second plurality of conductive strips.

7. The semiconductor package of claim 1 , further comprising an integrated fan-out (InFO) package, the InFO package comprising:
a die embedded in a molding material;
a redistribution structure on the die and the molding material, the redistribution structure being electrically coupled to the die, wherein a top redistribution layer of the redistribution structure comprises:
a third plurality of conductive patterns; and
a fourth plurality of conductive patterns interleaved with the third plurality of conductive patterns; and

a second UBM structure on the redistribution structure, the second UBM structure being electrically coupled to the top redistribution layer of the redistribution structure, the second UBM structure being bonded to the first UBM structure, the third plurality of conductive patterns being electrically coupled to the first plurality of conductive patterns through the second UBM structure, the fourth plurality of conductive patterns being electrically coupled to the second plurality of conductive patterns through the second UBM structure.

8. The semiconductor package of claim 7 , wherein the second UBM structure has a same size and a same shape as the first UBM structure.

9. The semiconductor package of claim 7 , wherein the second UBM structure of the InFO package comprises:
a third plurality of conductive strips electrically coupled to the first plurality of conductive strips of the first UBM structure; and
a fourth plurality of conductive strips electrically coupled to the second plurality of conductive strips of the first UBM structure, wherein each of the third plurality of conductive strips comprises discontinuous segments disposed along a line, and each of the fourth plurality of conductive strips comprises discontinuous segments disposed along a line.

10. The semiconductor package of claim 7 , wherein the third plurality of conductive patterns is parallel to the first plurality of conductive patterns, and the fourth plurality of conductive patterns is parallel to the second plurality of conductive patterns.

11. The semiconductor package of claim 7 , wherein the third plurality of conductive patterns is perpendicular to the first plurality of conductive patterns, and the fourth plurality of conductive patterns is perpendicular to the second plurality of conductive patterns.

12. A semiconductor package comprising:
an integrated passive device (IPD) comprising:
passive devices over a substrate;
an inter-connect structure over the passive devices and the substrate, a top metallization layer of the inter-connect structure having first metal patterns and second metal patterns parallel to the first metal patterns, the second metal patterns interleaved with the first metal patterns; and
a first under bump metallization (UBM) structure electrically coupled to the top metallization layer of the inter-connect structure, the inter-connect structure being between the substrate and the first UBM structure, the first UBM structure having first metal strips and second metal strips parallel to the first metal strips, the second metal strips interleaved with the first metal strips, the first metal strips being electrically coupled to the first metal patterns, and the second metal strips being electrically coupled to the second metal patterns; and

an integrated fan-out (InFO) package comprising:
a die embedded in a molding material;
a redistribution structure over the molding material, the redistribution structure electrically coupled to the die; and
a second UBM structure electrically coupled to the redistribution structure, a shape of the second UBM structure matching a shape of the first UBM structure, the second UBM structure being bonded to the first UBM structure.

13. The semiconductor package of claim 12 , wherein the first metal strips are parallel with the first metal patterns.

14. The semiconductor package of claim 12 , wherein the first metal strips are perpendicular to the first metal patterns.

15. The semiconductor package of claim 13 , wherein the first UBM structure of the IPD further comprises a third metal strip physically connected to the first metal strips, wherein the third metal strip is perpendicular to the first metal strips, and wherein a width of the third metal strip is larger than a width of at least one of the first metal strips.

16. The semiconductor package of claim 12 , wherein a top redistribution layer of the redistribution structure of the InFO package comprises third metal patterns and fourth metal patterns, and wherein a shape of the third metal patterns match a shap

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Chih
• Lai Chi-Hui
• Wu Ban-Li
• Tseng Ying-Cheng
• Kuo Ting-Ting
• Tai Chih-Hsuan
• Tsai Hao-Yi
• Wang Chuei-Tang
• Liu Chung-Shi
• Yu Chen-Hua
• Liu Chiahung

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title