Fiber coupler with an optical window
US-2019310431-A1 · Oct 10, 2019 · US
Carrier and integrated memory
US10840214B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10840214-B2 |
| Application number | US-201916546802-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2019 |
| Priority date | Apr 9, 2018 |
| Publication date | Nov 17, 2020 |
| Grant date | Nov 17, 2020 |
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- Title
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- Abstract
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- Assignees and inventors
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- Key dates
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- First independent claim
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- Citations and related patents
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Abstract
Official abstract text for this publication.
An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of accessing a memory within an integrated circuit (IC) device carrier, the memory joined to the IC device carrier by a dielectric material such that a contact surface of the memory is coplanar with a top surface of the dielectric material and coplanar with a top surface of the IC device carrier, the method comprising: sending, with an IC device connected to the top surface of the IC device carrier, an access instruction to store data within the memory through a first carrier interconnect, the first carrier interconnect directly upon the contact surface of the memory, directly upon the top surface of the dielectric material, and directly upon the top surface of the IC device carrier, wherein the first carrier interconnect electrically connects a signal contact of the memory and a wiring line within the IC device carrier; and providing, with a system board connected to a bottom surface of the IC device carrier, power potential through a second carrier interconnect directly upon the top surface of the dielectric material, wherein the second carrier interconnect electrically connects a power contact of the memory and a vertical interconnect access (VIA) that extends through the dielectric material. 2. The method of claim 1 , further comprising: storing the data within the memory. 3. A method of accessing a memory within an integrated circuit (IC) device carrier, the memory joined to the IC device carrier by a dielectric material such that a contact surface of the memory is coplanar with a top surface of the dielectric material and coplanar with a top surface of the IC device carrier, the method comprising: receiving, with an IC device connected to the top surface of the IC device carrier, data from the memory through a first carrier interconnect, the first carrier interconnect directly upon the contact surface of the memory, directly upon the top surface of the dielectric material, and directly upon the top surface of the IC device carrier, wherein the first carrier interconnect electrically connects a signal contact of the memory and a wiring line within the IC device carrier; and providing, with a system board connected to a bottom surface of the IC device carrier, power potential through a second carrier interconnect directly upon the top surface of the dielectric material, wherein the second carrier interconnect electrically connects a power contact of the memory and a vertical interconnect access (VIA) that extends through the dielectric material. 4. A method of accessing a memory within an integrated circuit (IC) device carrier, the memory comprising a contact surface that is coplanar with a top surface of the IC device carrier, the method comprising: sending, with a first IC device connected to the top surface of the IC device carrier, an access instruction to store data within the memory through a first carrier interconnect, the first carrier interconnect directly upon the contact surface of the memory and directly upon the top surface of the IC device carrier, wherein the first carrier interconnect electrically connects a signal contact of the memory and a contact of the first IC device; and providing, with a second IC device connected to the top surface of the IC device carrier, power potential to the memory through a second carrier interconnect, the second carrier interconnect directly upon the contact surface of the memory and directly upon the top surface of the IC device carrier, wherein the second carrier interconnect electrically connects a power contact of the memory and a contact of the second IC device. 5. The method of claim 4 wherein the memory lays within a recess of the IC device carrier.
Assignees
Inventors
Classifications
characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title
Through-vias · CPC title
for connecting multiple chips together · CPC title
Shapes or dispositions thereof · CPC title
comprising holes having chips therein · CPC title
Patent family
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Frequently asked questions
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- What does patent US10840214B2 cover?
- An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip …
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 17 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).