Vertical memory devices including stacked conductive lines and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10840183-B2
Application number	US-202016850391-A
Country	US
Kind code	B2
Filing date	Apr 16, 2020
Priority date	Dec 17, 2015
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate comprising opening regions extending in a first direction and a conductive line structure region between the opening regions, the conductive line structure region comprising a first region and a second region adjacent to each other in a second direction perpendicular to the first direction;
a conductive line structure on the conductive line structure region, the conductive line structure comprising first conductive lines spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein the conductive line structure on the first region comprises a first step structure comprising first steps, and the conductive line structure on the second region comprises a second step structure comprising second steps, and wherein heights of the second steps are different from heights of the first steps, respectively;
first contact plugs on upper surfaces of the first steps of the first step structure, respectively; and
second contact plugs on upper surfaces of the second steps of the second step structure, respectively,
wherein a distance in the second direction between the second step structure and the opening region being spaced apart from the second step structure is increased toward a bottom level of the second steps,
wherein exposed top surfaces of the first steps serves as first pad regions, respectively, and exposed top surfaces of the second steps serves as a second pad region, respectively, and wherein each of the first pad regions has a rounded corner at a boundary between the first and second regions, and
wherein the opening regions are parallel to each other, and the boundary between the first and second regions extends so as to not be parallel to an extending direction of each of the opening regions.

2. The vertical memory device of claim 1 , wherein heights of ones of the second steps are higher than heights of the first steps neighboring the ones of the second steps in the second direction.

3. The vertical memory device of claim 1 , wherein the widths in the second direction of the first pad regions increase from a top level toward a bottom level of the first steps, and wherein the widths in the second direction of the second pad regions decrease from a top level toward a bottom level of the second steps.

4. The vertical memory device of claim 2 , wherein each of the first pad regions has a shape of a rectangle having one rounded corner, in a plan view.

5. The vertical memory device of claim 1 , wherein an arrangement of the first contact plugs are parallel to the opening regions, and an arrangement of the second contact plugs are parallel to the opening regions.

6. The vertical memory device of claim 1 , wherein the first contact plugs are arranged in the first direction, and the second contact plugs are arranged in the first direction.

7. The vertical memory device of claim 1 , further comprising:
an insulating interlayer on the conductive line structure and the opening region.

8. The vertical memory device of claim 1 , wherein the conductive line structure further comprises a cell structure portion not having a stepped shape, and further comprising a vertical channel structure extending through the cell structure portion in the vertical direction.

9. The vertical memory device of claim 1 ,
wherein the conductive line structure include a plurality of conductive line structures, and
wherein the plurality of conductive line structures are symmetrical to each other with respect to the opening.

10. A vertical memory device, comprising:
a substrate comprising opening regions extending in a first direction and a conductive line structure region between the opening regions, the conductive line structure region comprising a first region and a second region adjacent to each other in a second direction perpendicular to the first direction;
a conductive line structure on the conductive line structure region, the conductive line structure comprising first conductive lines spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein the conductive line structure on the first region comprises a first step structure comprising first steps, and the conductive line structure on the second region comprises a second step structure comprising second steps, and wherein heights of the second steps are different from heights of the first steps, respectively;
an insulating interlayer on the conductive line structure and the opening region;
first contact plugs through the insulating interlayer, the first contact plugs on upper surfaces of the first steps of the first step structure, respectively; and
second contact plugs through the insulating interlayer, the second contact plugs on upper surfaces of the second steps of the second step structure, respectively,
wherein a distance in the second direction between the second step structure and the opening region being spaced apart from the second step structure is increased toward a bottom level of the second steps,
wherein an arrangement of the first contact plugs are parallel to the opening regions, and an arrangement of the second contact plugs are parallel to the opening regions, and
wherein the opening regions are parallel to each other, and the boundary between the first and second regions extends so as to not be parallel to an extending direction of each of the opening regions.

11. The vertical memory device of claim 10 , wherein heights of ones of the second steps are higher than heights of the first steps neighboring the ones of the second steps in the second direction.

12. The vertical memory device of claim 11 ,
wherein exposed top surfaces of the first steps serve as first pad regions, respectively, and
wherein each of the first pad regions has a rounded corner at a boundary between the first and second regions.

13. The vertical memory device of claim 11 , wherein each of the first pad regions has a shape of a rectangle having one rounded corner, in a plan view.

14. The vertical memory device of claim 10 , wherein the first contact plugs are arranged in the first direction, and the second contact plugs are arranged in the first direction.

15. A vertical memory device, comprising:
a substrate comprising opening regions extending in a first direction and a conductive line structure region between the opening regions, the conductive line structure region comprising a first region to a n-th region, wherein n is a natural number of 2 or more, wherein the first region to the n-th region are adjacent to each other in a second direction perpendicular to the first direction;
a conductive line structure on the conductive line structure region, the conductive line structure comprising first conductive lines spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, wherein the conductive line structure on the first region comprises a first step structure comprising first steps, and the conductive line structure on the n-th region comprises an n-th step structure comprising n-th steps, and wherein heights of the n-th steps are different from heights of n-1-th steps, respectively;
first contact plugs on upper surfaces of the first steps, respectively; and
n-th contact plugs on upper surfaces of the n-th steps of the n-th step structure, respectively,
wherein the opening regions are parallel to each other, and a boundary between neighboring regions among the first region to the n-th region extends so as to not be parall

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Seok-Jung
• Lee Sung-Hun
• Han Jee-Hoon
• Chung Yong-Won
• Cho Seong Soon

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L23/5226

  Electricity · mapped topic