Circuit having a low power charge pump for storing information in non-volatile memory during a loss of power event

Patent metadata

Field	Value
Publication number	US-10839920-B2
Application number	US-201916543867-A
Country	US
Kind code	B2
Filing date	Aug 19, 2019
Priority date	Sep 29, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A data storage circuit for storing data from volatile memory to non-volatile memory is powered by a low power charge pump circuit that is independent of the power for the volatile memory and that is activated upon power loss. The low power charge pump circuit includes an amplifier, a voltage-controlled oscillator, a charge pump core, and a voltage divider. The amplifier outputs a current according to a voltage difference between a reference input voltage and a feedback voltage output from the voltage divider. The current is converted to a voltage that controls the oscillator, which outputs a series of pulses to power the charge pump core. The charge pump core in turn provides the output voltage, which may be used to power an attached load. The attached load may be a programming port for an EEPROM.

First claim

What is claimed is:

1. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:
a non-volatile matrix of memory cells comprising a plurality of rows and a plurality of columns of memory cells including an independent row of memory cells; and
a controller comprising a plurality of drivers including row and column drivers and an independent driver, the controller configured to:
in the absence of a power loss, write data from the volatile memory to the non-volatile matrix of memory cells by utilizing the row and column drivers to perform collective row and column operations; and
in response to receiving a power loss signal, write data from said volatile memory to said independent row of memory cells by selectively supplying energy to the independent row driver, and not the row and column drivers, from a low power charge pump circuit;

wherein the low power charge pump circuit comprises:
an amplifier configured to provide at an amplifier output a signal having an electrical characteristic that is proportional to a voltage difference between a reference voltage and a feedback voltage;
a voltage-controlled oscillator (VCO) having an input coupled to the amplifier output, the VCO configured to provide at a VCO output a series of electrical pulses according to a pulse frequency that is proportional to the amplifier output signal;
a charge pump core having an input coupled to the VCO output, the charge pump core configured to provide an output voltage for the low power charge pump circuit according to energy received from the series of electrical pulses; and
a voltage scaler, coupled to the output voltage for the low power charge pump circuit, the voltage scaler configured to produce the feedback voltage as a fraction of the output voltage for the low power charge pump circuit.

2. The circuit according to claim 1 , wherein the amplifier comprises a transconductance amplifier.

3. The circuit according to claim 1 , wherein the reference voltage comprises a bandgap voltage reference.

4. The circuit according to claim 1 , wherein the voltage-controlled oscillator outputs the series of electrical pulses as rectangular waves.

5. The circuit according to claim 1 , wherein a maximum pulse frequency of the series of electrical pulses is approximately 700 kilohertz.

6. The circuit according to claim 1 , wherein a steady state pulse frequency of the series of electrical pulses is approximately 20 kilohertz.

7. The circuit according to claim 1 , wherein the average output voltage at a steady state is approximately 14.5 volts.

8. The circuit according to claim 1 , wherein a rise time between the output voltage being zero and the average output voltage having a steady state is approximately 200 microseconds.

9. The circuit according to claim 1 , wherein the low power charge pump circuit comprises a switch that actuates, according to the power loss signal, to couple the reference voltage to the amplifier.

10. The circuit according to claim 1 , wherein the non-volatile matrix of memory cells comprises an electrically erasable programmable read only memory (EEPROM).

11. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:
storage means comprising a plurality of rows and a plurality of columns of memory cells including an independent row of memory cells; and
controller means comprising a plurality of drivers including row and column drivers and an independent driver, the controller configured to:
in the absence of a power loss, write data from the volatile memory to the storage means by utilizing the row and column drivers to perform collective row and column operations; and
in response to receiving a power loss signal, write data from said volatile memory to said independent row of memory cells by selectively supplying energy to the independent row driver, and not the row and column drivers, from a low power charge pump circuit;

wherein the low power charge pump circuit comprises:
first means configured to provide at a first means output a signal having an electrical characteristic that is proportional to a voltage difference between a reference voltage and a feedback voltage;
second means having an input coupled to the first means output, the second means configured to provide at a second means output a series of electrical pulses according to a pulse frequency that is proportional to the amplifier output signal;
third means having an input coupled to the second means output, the third means configured to provide an output voltage for the low power charge pump circuit according to energy received from the series of electrical pulses; and
fourth means, coupled to the output voltage for the low power charge pump circuit, the fourth means configured to produce the feedback voltage as a fraction of the output voltage for the low power charge pump circuit.

12. The circuit according to claim 11 , wherein the first means comprise a transconductance amplifier.

13. The circuit according to claim 11 , wherein the reference voltage comprises a bandgap voltage reference.

14. The circuit according to claim 11 , wherein the second means output the series of electrical pulses as rectangular waves.

15. The circuit according to claim 11 , wherein a maximum pulse frequency of the series of electrical pulses is approximately 700 kilohertz.

16. The circuit according to claim 11 , wherein a steady state pulse frequency of the series of electrical pulses is approximately 20 kilohertz.

17. The circuit according to claim 11 , wherein the average output voltage at a steady state is approximately 14.5 volts.

18. The circuit according to claim 11 , wherein a rise time between the output voltage being zero and the average output voltage having a steady state is approximately 200 microseconds.

19. The circuit according to claim 11 , wherein the low power charge pump circuit comprises switching means that actuate, according to the power loss signal, to couple the reference voltage to the first means.

20. The circuit according to claim 11 , wherein the storage means comprise an electrically erasable programmable read only memory (EEPROM).

Assignees

• Allegro Microsystems Llc

Inventors

• Cesaretti Juan Manuel
• Osinaga Javier

Classifications

• G11C14/0018

  whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• B62D5/0457

  characterised by control features of the drive means as such · CPC title