Circuits and methods for fault testing

Patent metadata

Field	Value
Publication number	US-9513337-B2
Application number	US-201113290293-A
Country	US
Kind code	B2
Filing date	Nov 7, 2011
Priority date	Nov 7, 2011
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.

First claim

What is claimed is:

1. An integrated circuit sensor comprising:
an oscillator for generating a master clock signal that is used by the integrated circuit sensor both when the integrated circuit sensor is functioning in a test mode and when the integrated circuit sensor is functioning in a normal operational mode, wherein, when the integrated circuit sensor is functioning in a test mode, a frequency of the master clock signal is based at least in part on an externally generated programming signal provided to the integrated circuit sensor;
a fault test clock signal generator responsive to the master clock signal and to a test trigger signal, the fault test clock signal generator configured to generate, during test of the integrated circuit sensor when the integrated circuit sensor is functioning in its test mode, a test clock signal derived at least in part from the master clock signal, wherein the test clock signal comprises a launch pulse and a capture pulse used during at least a portion of delay fault testing of the integrated circuit sensor, the launch and capture pulses having a controllable time spacing between an edge of the launch pulse and an edge of the capture pulse, wherein different values of the controllable time spacing are usable for different fault tests, and wherein the controllable time spacing is controlled based at least in part on information conveyed via the externally generated programming signal; and
an output processor responsive to the master clock signal and to information provided by the integrated circuit sensor relating to a ferromagnetic article disposed in proximity to the integrated circuit sensor when the integrated circuit sensor is functioning in its normal operational mode, the output processor providing, a sensor output signal indicative of one or more characteristics of the article.

2. The integrated circuit sensor of claim 1 wherein the launch pulse and the capture pulse of the test clock signal have rising and falling edges that substantially coincide with like edges of consecutive pulses of the master clock signal.

3. The integrated circuit sensor of claim 1 wherein the oscillator is responsive to a trim signal for adjusting the master clock signal.

4. The integrated circuit sensor of claim 3 wherein the trim signal is based on a measurement of the master clock signal in order to calibrate the master clock signal.

5. The integrated circuit sensor of claim 3 further comprising a fault test programming circuit for generating a test mode selection signal, wherein the fault test clock signal generator is further responsive to the test mode selection signal for generating the test clock signal.

6. The integrated circuit sensor of claim 5 wherein the fault test programming circuit comprises a multiplexer having a first input responsive to a scan clock signal, a second input responsive to the master clock signal, and an output at which the test trigger signal is provided, wherein the multiplexer is responsive to a test mode enable signal for providing a selected one of the scan clock signal and the master clock signal as the test trigger signal.

7. The integrated circuit sensor of claim 5 wherein the fault test programming circuit further comprises a decoder for generating the trim signal in response to the externally generated programming signal.

8. The integrated circuit sensor of claim 1 wherein the sensor output signal is indicative of a direction of rotation of the ferromagnetic article proximate to the integrated circuit sensor.

9. The integrated circuit sensor of claim 8 wherein the direction of rotation is indicated by a pulse width established by the master clock signal.

10. The integrated circuit sensor of claim 1 wherein the externally generated programming signal is superimposed on a power signal used to provide operational power to the integrated circuit sensor.

11. The integrated circuit sensor of claim 1 wherein the externally generated programming signal comprises a data input signal from an automated test pattern generator (ATPG), wherein the oscillator generates the master clock signal at least partially in accordance with information appended to the data signal provided by the ATPG.

12. An integrated circuit sensor comprising:
an oscillator for generating a master clock signal used by the integrated circuit sensor both when the integrated circuit is functioning in a test mode and when the integrated circuit sensor is functioning in a normal operational mode, wherein, when the integrated circuit sensor is functioning in a test mode, a frequency of the master clock signal is based at least in part on an externally generated programming signal provided to the integrated circuit sensor; and
a fault test clock signal generator responsive to the master clock signal and to a test trigger signal for generating, during test of the integrated circuit sensor and when the integrated circuit sensor is functioning in its test mode, a test clock signal derived at least in part from the master clock signal, wherein the test clock signal comprises a launch pulse and a capture pulse used during at least a portion of delay fault testing of the integrated circuit sensor, the launch and capture pulses having rising and falling edges that substantially coincide with like edges of consecutive pulses of the master clock signal and having a controllable time spacing between an edge of the launch pulse and an edge of the capture pulse, wherein different values of the controllable time spacing are used for different fault tests and wherein the controllable time spacing is controlled based at least in part on information conveyed via the externally generated programming signal.

13. The integrated circuit sensor of claim 12 further comprising an output processor responsive to the master clock signal and to information relating to a ferromagnetic article disposed in proximity to the integrated circuit sensor when the integrated circuit sensor is functioning in normal operational mode, the output processor providing a sensor output signal indicative of one or more characteristics of the ferromagnetic article.

14. The integrated circuit sensor of claim 12 wherein the oscillator is responsive to a trim signal for adjusting the master clock signal.

15. A method, comprising:
generating, using an oscillator built into an integrated circuit sensor, a master clock signal used by the integrated circuit sensor both when the integrated circuit sensor is functioning in a test mode and when the integrated circuit sensor is functioning in a normal operational mode, wherein, when the integrated circuit sensor is functioning in a test mode, a frequency of the master clock signal is based at least in part on an externally generated programming signal provided to the integrated circuit sensor;
generating, during at least a portion of the testing of the integrated circuit sensor when functioning in test mode, a test clock signal, the test clock signal generated in response to the master clock signal and a test trigger signal, wherein the test clock signal is derived at least in part from the master clock signal and comprises a launch pulse and a capture pulse used during at least a portion of delay fault testing of the integrated circuit sensor, the launch and capture pulses having a controllable time spacing between an edge of the launch pulse and an edge of the capture pulse, wherein different values of the controllable time spacing are used for different fault tests and wherein the controllable time spacing is controlled based at least in part on information conveyed via the externally generated programming signal

Assignees

• Forrest Glenn A
• Cook Aaron
• Briere Dana
• Fernandez Devon
• Nakayama Naota
• Allegro Microsystems Llc

Inventors

• Forrest Glenn A
• Cook Aaron
• Briere Dana
• Fernandez Devon
• Nakayama Naota

Classifications

• G01R31/318594

  Timing aspects (clock circuits G01R31/318552) · CPC title

• G01R31/318552 Primary

  Clock circuits details · CPC title