System and method to extend NVME queues to user space

Patent metadata

Field	Value
Publication number	US-10838852-B2
Application number	US-201514862145-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Apr 17, 2015
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

An embodiment includes a system, comprising: a processor configured to: read a stride parameter from a device coupled to the processor; and map registers associated with the device into virtual memory based on the stride parameter; wherein: the stride parameter is configured to indicate a stride between the registers associated with the device; and the processor is configured to map at least one of the registers to user space virtual memory in response to the stride parameter.

First claim

The invention claimed is:

1. A system, comprising:
a non-volatile memory express (NVMe) device comprising a memory and a plurality of registers, a stride parameter being stored in the memory that indicates a stride between each of the plurality of registers, the plurality of registers comprising at least one pair of first registers that are mappable into a kernel space and at least one pair of second registers that are mappable into a user space, each pair of first registers comprising a submission queue doorbell register and a completion queue doorbell register, and each pair of second registers comprising a submission queue doorbell register and a completion queue doorbell register that are adjacent to each other in the user space; and
a processor coupled to a processor-local bus, the processor:
reading the stride parameter stored in the memory of the NVMe device through the processor-local bus; and
mapping the first registers into the kernel space and the second registers into the user space based on the stride parameter, the at least one pair of first registers being separated in kernel space by the stride parameter and the at least one pair of second registers being separated in user space by the stride parameter.

2. The system of claim 1 , wherein registers of a first pair of first registers are adjacent to each other in the kernel space.

3. The system of claim 2 , wherein the plurality of registers comprises a first predetermined number of first registers, and the processor comprises a second predetermined number of processing entities, and
wherein the first predetermined number is greater than the second predetermined number.

4. The system of claim 2 , wherein the processor-local bus comprises a Peripheral Component Interconnect Express (PCIe) bus.

5. The system of claim 2 , wherein a value of the stride parameter is greater than or equal to a page size in the user space.

6. The system of claim 2 , wherein a value of the stride parameter is greater than a size of the registers of the plurality of registers.

7. The system of claim 2 , wherein a value of the stride parameter is less than a page size in the user space.

8. The system of claim 2 , wherein a value of the stride parameter places a pair of second registers into a single page of the user space.

9. The system of claim 2 , wherein:
the processor further presents a virtual machine; and
at least one pair of second registers is mapped into a virtual memory associated with the virtual machine.

10. The system of claim 2 , wherein the processor further maps the second registers to be accessible by a user space application without intervening kernel layers.

11. A method, comprising:
reading, by a processor, a stride parameter stored in a memory of a non-volatile memory express (NVMe) device coupled to a processor-local bus, the NVMe device comprising the memory and a plurality of registers, a stride parameter indicating a stride between each of the plurality of registers, the plurality of registers comprising at least one pair of first registers that are mappable into a kernel space and at least one pair of second registers that are mappable into a user space, each pair of first registers comprising a submission queue doorbell register and a completion queue doorbell register, and each pair of second registers comprising a submission queue doorbell register and a completion queue doorbell register that are adjacent to each other in the user space; and
mapping, by the processor, the first registers into the kernel space and the second registers into the user space based on the stride parameter, the at least one pair of first registers being separated in kernel space by the stride parameter and the at least one pair of second registers being separated in user space by the stride parameter.

12. The method of claim 11 , wherein registers of a first pair of first registers are adjacent to each other in the kernel space.

13. The method of claim 12 , wherein a value of the stride parameter is greater than or equal to a page size in the user space.

14. The method of claim 12 , wherein a value of the stride parameter is less than a page size in the user space.

15. The method of claim 12 , further comprising:
presenting a virtual machine; and
wherein mapping the at least one pair of second registers comprises mapping the at least one pair of second registers into a virtual memory associated with the virtual machine.

16. A non-volatile memory express (NVMe) device, comprising:
a memory that stores data;
a plurality of registers comprising at least one pair of first registers that are mappable into a kernel space and at least one pair of second registers that are mappable into a user space, each pair of first registers comprising a submission queue doorbell register and a completion queue doorbell register, each pair of second registers comprising a submission queue doorbell register and a completion queue doorbell register, and registers of a first pair of second registers being adjacent to each other in the user space; and
a stride register that stores a stride parameter that indicates a separation between the at least one pair of first registers in kernel space and a separation between the at least one pair of registers in user space.

17. The NVMe device of claim 16 , wherein registers of a pair of first registers are adjacent to each other in the kernel space.

18. The NVMe device of claim 17 , wherein a value of the stride parameter is greater than or equal to a page size in the user space.

19. The NVMe device of claim 17 , wherein a value of the stride parameter is less than a page size in the user space.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Pinto Oscar Prem

Classifications

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/202

  Non-volatile memory · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/0238 Primary

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F13/4068

  Electrical coupling · CPC title