Burn-in preform and method of making the same

Patent metadata

Field	Value
Publication number	US-10838002-B2
Application number	US-201816175460-A
Country	US
Kind code	B2
Filing date	Oct 30, 2018
Priority date	Oct 30, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Some implementations are directed to a burn-in solder preform including: a barrier layer to prevent thermally conductive material from adhering to a semiconductor component during burn-in testing; and a thermally conductive cladding layer attached to a portion of the barrier layer such that at least one dimension of the barrier layer extends past the thermally conductive cladding layer, where the thermally conductive cladding layer is attached over the barrier layer through continuous attachment or spot attachment. In some implementations, a method includes: placing the aforementioned burn-in solder preform between a test fixture and a semiconductor component; attaching a portion of the barrier layer of the burn-in solder preform to a head of the text fixture; and after attaching a portion of the barrier layer of the burn-in solder preform to the head of the test fixture, performing burn-in testing of the semiconductor component.

First claim

What is claimed is:

1. A burn-in solder preform comprising:
a barrier layer configured to prevent thermally conductive material of a thermally conductive cladding layer from adhering to a semiconductor component, wherein one or more first portions of the barrier layer not covered by the thermally conductive cladding layer are configured to be folded around and attached to a head of a test fixture used to perform burn-in testing of the semiconductor component; and
the thermally conductive cladding layer attached over a center portion of the barrier layer, the thermally conductive cladding layer dimensioned such that it does not extend past the center portion and such that the one or more first portions of the barrier layer extend past the thermally conductive cladding layer, wherein the thermally conductive cladding layer is attached over the barrier layer through continuous or spot attachment.

2. The burn-in solder preform of claim 1 , wherein the continuous attachment comprises mechanical attachment around all or part of an outer edge of the thermally conductive cladding layer.

3. The burn-in solder preform of claim 2 , wherein the mechanical attachment comprises pressure attachment.

4. The burn-in solder preform of claim 1 , wherein the spot attachment comprises mechanical attachment around all or part of an outer edge of the thermally conductive cladding layer.

5. The burn-in solder preform of claim 1 , wherein the barrier layer is comprised of a metal or a metal alloy.

6. The burn-in solder preform of claim 5 , wherein the barrier layer comprises aluminum (Al), an aluminum alloy, copper (Cu), a copper-zinc alloy, or a combination thereof.

7. The burn-in solder preform of claim 5 , wherein the barrier layer comprises Al or an Al alloy, and wherein the thermally conductive cladding layer comprises indium (In) or an In alloy.

8. The burn-in solder preform of claim 7 , wherein the thermally conductive cladding layer is spot attached along edges to the barrier layer.

9. The burn-in solder preform of claim 8 , wherein the preform consists of the barrier layer and the thermally conductive cladding layer.

10. A method of making a burn-in solder preform, the method comprising: continuously attaching or spot attaching a thermally conductive cladding layer over a center portion of a barrier layer such that one or more other portions of the barrier layer extend past the thermally conductive cladding layer and are not covered by the thermally conductive cladding layer, wherein the thermally conductive cladding layer is dimensioned such that it does not extend past the center portion of the barrier layer, wherein the one or more other portions of the barrier layer are configured to be folded around and attached to a head of a test fixture used to perform burn-in testing of a semiconductor component, wherein the barrier layer is configured to prevent thermally conductive material of the thermally conductive cladding layer from adhering to the semiconductor component.

11. The method of claim 10 , wherein the barrier layer is continuously attached around all or part of the outer edge of the thermally conductive cladding layer.

12. The method of claim 10 , wherein the barrier layer is spot attached around all or part of the outer edge of the thermally conductive cladding layer.

13. The method of claim 10 , wherein the barrier layer comprises a metal or metal alloy.

14. The method of claim 13 , wherein the barrier layer comprises aluminum (Al), an aluminum alloy, copper (Cu), a copper-zinc alloy, or a combination thereof.

15. The method of claim 10 , wherein the thermally conductive cladding layer comprises a metal or metal alloy.

16. The method of claim 15 , wherein the thermally conductive cladding layer comprises indium (In), an indium alloy, a tin (Sb), tin alloy, lead (Pb), gold (Au), silver (Ag), gallium (Ga), germanium (Ge), or a combination thereof.

17. A method, comprising:
attaching a thermally conductive cladding layer over a center of a barrier layer to form a burn-in solder preform, wherein after attachment, at least one dimension of the barrier layer extends past the thermally conductive cladding layer;
placing the burn-in solder preform between a test fixture and a semiconductor component;
attaching the portion of the barrier layer of the burn-in solder preform to a head of the test fixture; and
after attaching the portion of the barrier layer of the burn-in solder preform to the head of the test fixture, performing burn-in testing of the semiconductor component.

18. The method of claim 17 , wherein attaching the portion of the barrier layer to the head of the text fixture, comprises: folding up portions of the barrier layer not covered with the thermally conductive cladding layer to attach to the head of the test fixture.

19. The method of claim 17 , wherein the semiconductor component is a microprocessor chip, wherein the test fixture comprises a plurality of resistance temperature detectors (RTDs).

20. The method of claim 17 , wherein the barrier layer comprises aluminum or an aluminum alloy, wherein the thermally conductive cladding layer comprises indium or an indium alloy.

Assignees

• Indium Corp

Inventors

• Gross Thomas R
• Jarrett Robert
• Lanza Jr Anthony D
• Merritt Craig K

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• G01R31/2863 Primary

  Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04) · CPC title

• G01R31/2872 Primary

  related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation · CPC title