Creating inductors, resistors, capacitors and other structures in printed circuit board vias with light pipe technology
US-2019239358-A1 · Aug 1, 2019 · US
Creating in-via routing with a light pipe
US10834830B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10834830-B2 |
| Application number | US-201916274565-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 13, 2019 |
| Priority date | Feb 13, 2019 |
| Publication date | Nov 10, 2020 |
| Grant date | Nov 10, 2020 |
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- Title
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- Abstract
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- Assignees and inventors
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- Key dates
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- First independent claim
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- CPC / IPC classifications
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- Citations and related patents
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Abstract
Official abstract text for this publication.
Creating in-via routing with a light pipe is disclosed. A resist layer is applied over a layer of conductive material provided in a via. A light pipe is inserted into the via. The surface of the light pipe includes at least one masked portion and at least one unmasked portion. A portion of the resist layer is exposed with light emitted from the unmasked portions of the light pipe. Portions of the conductive layer corresponding to the exposed portion of the resist layer are then removed to create the in-via routing.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of creating in-via routing with a light pipe, the method comprising: applying a resist layer over a layer of conductive material provided in a via of a printed circuit board (PCB) comprising a plurality of PCB layers; inserting the light pipe into the via, wherein the surface of the light pipe includes at least one masked portion and at least one unmasked portion; exposing a portion of the resist layer with light emitted from the at least one unmasked portion of the light pipe; and removing a portion of the conductive layer corresponding to the exposed portion of the resist layer, wherein removing the portion of the conductor layer removes an electrical connection between at least two of the plurality of PCB layers, while intersecting at least two conductive traces. 2. The method of claim 1 wherein applying a resist layer over a layer of conductive material provided in a via includes providing the via, wherein the via has been plated with the conductive material. 3. The method of claim 1 wherein removing a portion of the conductive layer corresponding to the exposed portion of the resist layer includes etching the via with acid. 4. The method of claim 1 wherein the resist layer is a positive photoresist material. 5. The method of claim 1 wherein removing a portion of the conductive layer corresponding to the exposed portion of the resist layer includes creating at least two independent connections in the via. 6. The method of claim 1 wherein removing a portion of the conductive layer corresponding to the exposed portion of the resist layer includes removing a conductive stub between a conductive pad on a surface of the printed circuit board and a conductive trace in an interior layer of the printed circuit board. 7. The method of claim 1 wherein removing a portion of the conductive layer corresponding to the exposed portion of the resist layer includes removing partially removing conductive material between a first conductor in a first interior layer of the printed circuit board and a second conductor in a second interior layer of the circuit board.
Assignees
Inventors
Classifications
- H05K3/429Primary
Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title
Patterning on via walls; Plural lands around one hole · CPC title
- H05K3/4673Primary
Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer (similar methods for protective coatings H05K3/28) · CPC title
Plating · CPC title
by forming conductive walled aperture in base · CPC title
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Frequently asked questions
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- What does patent US10834830B2 cover?
- Creating in-via routing with a light pipe is disclosed. A resist layer is applied over a layer of conductive material provided in a via. A light pipe is inserted into the via. The surface of the light pipe includes at least one masked portion and at least one unmasked portion. A portion of the resist layer is exposed with light emitted from the unmasked portions of the light pipe. Portions of t…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H05K3/429. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 10 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).