Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors

Patent metadata

Field	Value
Publication number	US-10834352-B2
Application number	US-201916247475-A
Country	US
Kind code	B2
Filing date	Jan 14, 2019
Priority date	Jan 14, 2019
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

An image sensor has an array of pixels configured in multiple blocks; each block coupled to a separate analog-to-digital converter (ADC) to provide digitized image data. The ADCs feed digitized images into an image RAM; and the image RAM feeds digitized images to an alignment buffer in a first pixel order. The alignment buffer provides digitized images to an image processor in a second pixel order different from the first pixel order. In an embodiment, the alignment buffer uses a multiport RAM. In another embodiment, the alignment buffer uses first and second alignment buffer RAMs, writing one alignment buffer RAM while reading the other alignment buffer RAM to provide image data to the image processor. In embodiments, the alignment buffer provides digitized images in an order selectable between a full resolution and a reduced resolution order, and selectable between a right-to-left and left-to-right order.

First claim

What is claimed is:

1. An image sensor comprising:
an array of pixels configured to sense light and configured in a plurality of blocks;
where each block of pixels is coupled to a separate analog-to-digital converter (ADC) adapted to provide digitized image data;
the ADCs being coupled to feed digitized image data into an image RAM; and
the image RAM is coupled to provide digitized image data to an alignment buffer in a first pixel order;
where the alignment buffer is configured to provide digitized image data to an image processor in a second pixel order, the second pixel order different from the first pixel order, the array of pixels, and the image processor are each physically located on a separate die, in a stacked-die assembly the separate die being interconnected by die-to-die bonds;
wherein the array of pixels, the ADCs, and the image RAM are each physically located on separate die of the stacked-die assembly;
and wherein the image processor is located on the same die as the ADCs.

2. The image sensor of claim 1 wherein the alignment buffer comprises a multiport RAM capable of being read at a first address and written at a second address simultaneously, the first address being different from the second address.

3. An image sensor comprising:
an array of pixels configured to sense light and configured in a plurality of blocks;

where each block of pixels is coupled to a separate analog-to-digital converter (ADC) adapted to provide digitized image data;
the ADCs being coupled to feed digitized image data into an image RAM; and

the image RAM is coupled to provide digitized image data to an alignment buffer in a first pixel order;
where the array of pixels, the ADCs, and the image RAM are each physically located on a separate die, the separate die being interconnected by die-to-die bonds;
where the alignment buffer is configured to provide digitized image data to an image processor in a second pixel order, the second pixel order different from the first pixel order;

wherein the alignment buffer comprises a multiport RAM capable of being read at a first address and written at a second address simultaneously, the first address being different from the second address; and
wherein the multiport RAM is configured to be written in words of a first length and to be read in words of a second length shorter than the first length.

4. The image sensor of claim 3 wherein the second pixel order is configurable to at least a left-to-right and a right-to-left pixel order.

5. The image sensor of claim 4 wherein the second pixel order is configurable to at least a full resolution pixel order and to a reduced resolution pixel order.

6. The image sensor of claim 5 wherein the image RAM is DRAM and is adapted to store at least one entire image frame.

7. The image sensor of claim 3 wherein the alignment buffer comprises a first and a second alignment buffer RAM, the alignment buffer being configured to write the first alignment buffer RAM with digitized image data while the second alignment buffer RAM is read to provide digitized image data to the image processor, and to write the second alignment buffer RAM with digitized image data while the first alignment buffer RAM is read to provide digitized image data to the image processor.

8. The image sensor of claim 7 wherein the image RAM is DRAM and is adapted to store at least one entire image frame.

9. The image sensor of claim 8 wherein the alignment buffer is reconfigurable to provide the digitized image data to the image processor in an order selectable from at least a left-to-right pixel order and a right-to-left pixel order.

10. The image sensor of claim 9 wherein the multiport RAM is configured to be written in words of a first length and to be read in words of a second length shorter than the first length.

11. The image sensor of claim 10 wherein the alignment buffer is configurable to provide digitized image data to the image processor in a full resolution order and in a reduced resolution order.

12. A method of providing image data to an image processor in a multiple-stacked-wafer image sensor, the image sensor having a pixel sensor die having pixels organized as blocks of pixels, comprising:
repetitively reading pixel data from a pixel in each block of pixels through an analog-to-digital converter (ADC) to generate digitized pixel data and simultaneously writing the digitized pixel data for the pixel in each block into an image RAM until all pixels in each block are read;
reading the digitized pixel data from the image RAM located on a separate wafer from the ADC into an alignment buffer, the pixel data being in a first pixel order in the image RAM; and
reading the digitized pixel data from the alignment buffer into an image processor in a second pixel order;
the image processor the image processor being located on the same wafer as the ADCs and on a different wafer than the pixel array.

13. The method of claim 12 wherein the second pixel order provides digitized pixel data of pixels of color cells to the image processor in color cell groups.

Assignees

• Omnivision Tech Inc

Inventors

• Qin Qing
• Ryu Hoon
• Jung Taehyung

Classifications

• H04N25/79 Primary

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title