CMOS image sensor (CIS) including MRAM (magnetic random access memory)

Patent metadata

Field	Value
Publication number	US-10157951-B2
Application number	US-201715676069-A
Country	US
Kind code	B2
Filing date	Aug 14, 2017
Priority date	Jan 13, 2017
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

First claim

What is claimed is:

1. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) comprising:
an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure; and
a lower chip, on which the upper chip is mounted, the lower chip comprising a logic region having arranged therein logic circuits and a memory region having embedded therein magnetic random access memory (MRAM),
wherein one or more of the logic circuits are configured to generate image data in response to signals received from the upper chip and to operate the MRAM as an image buffer memory for storing the image data generated by the logic region
wherein the MRAM comprises unit cells including cell transistors and magnetic tunnel junction (MTJ) structures, the unit cells being arranged in the memory region in a two-dimensional array structure,
wherein the cell transistors are arranged on the same level as transistors of the logic region,
wherein each MTJ structure comprises a pinned layer, a tunnel layer, and a free layer,
wherein each MTJ structure is positioned between two wire layers adjacent to each other from among a plurality of wire layers arranged above the cell transistors, and
wherein the MTJ structures are positioned between a wire layer forming a plurality of bit lines and a wire layer connected to drain regions of the cell transistors.

2. The CIS of claim 1 , wherein the CIS is configured to operate according to a rolling shutter scheme for reading out data of the pixels row-by-row.

3. The CIS of claim 1 ,
wherein the logic region comprises an analog signal processing circuit configured to process analog pixel signals received from the pixels of the upper chip, an analog-to-digital converter (ADC) circuit configured to convert an analog signal from the analog signal processing circuit into the image data, wherein the image data is a digital signal, and an image signal processing circuit configured to process the image data, and
wherein the MRAM is configured to store the image data and transfer the image data to the image signal processing circuit.

4. The CIS of claim 1 , wherein the MRAM is configured to store the image data as frame images.

5. The CIS of claim 1 ,
wherein a plurality of through substrate vias (TSVs) are formed in the upper chip, and
wiring of the upper chip is electrically connected to wiring of the lower chip via the TSVs.

6. The CIS of claim 1 , wherein wiring of the upper chip is electrically connected to wiring of the lower chip via Cu—Cu direct bonding.

7. The CIS of claim 1 ,
wherein, in the upper chip, color filters and micro-lenses are formed on a backside surface of a semiconductor substrate of the upper chip, wherein wire layers are arranged on a frontside surface of the semiconductor substrate, and
wherein the upper chip is stacked on the lower chip such that the backside surface of the semiconductor substrate faces upward and the frontside surface of the semiconductor substrate faces toward the lower chip.

8. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) comprising:
an upper chip comprising a plurality of pixels arranged in a two-dimensional array structure and first wire layers arranged below the pixels, wherein each of the plurality of pixels comprises a photodiode and pixel transistors; and
a lower chip on which the upper chip is mounted, the lower chip comprising a logic region having logic circuits formed therein, second wire layers and a memory region having a magnetic random access memory (MRAM) cells,
wherein the first wire layers are electrically connected to the second wire layers, and
wherein the MRAM is configured to operate as an image buffer memory for storing image data processed by logic circuits of the logic region,
wherein the MRAM comprises unit cells including cell transistors and magnetic tunnel junction (MTJ) structures, the unit cells being arranged in the memory region in a two-dimensional array structure,
wherein the cell transistors are arranged on the same level as transistors of the logic region,
wherein each MTJ structure comprises a pinned layer, a tunnel layer, and a free layer,
wherein each MTJ structure is positioned between two wire layers adjacent to each other from among a plurality of wire layers arranged above the cell transistors, and
wherein the MTJ structures are positioned between a wire layer forming a plurality of bit lines and a wire layer connected to drain regions of the cell transistors.

9. The CIS of claim 8 ,
wherein through substrate vias (TSVs) are formed in at a portion of the upper chip that does not include the pixels, and
wherein the first wire layers are electrically connected to the second wire layers via the TSVs.

10. The CIS of claim 8 , wherein the first wire layers are electrically connected to the second wire layers via Cu—Cu direct bonding.

11. The CIS of claim 8 ,
wherein the CIS is configured to operate according to a rolling shutter scheme for reading out data of the pixels row-by-row,
wherein the logic circuits constitute an analog signal processing circuit configured to process analog pixel signals received from pixels of the upper chip, an analog-to-digital converter (ADC) circuit configured to convert an analog signal from the analog signal processing circuit into the image data, wherein the image data is a digital signal, and an image signal processing circuit configured to process the image data, and
wherein the MRAM is configured to store the image data and transfer the image data to the image signal processing circuit.

12. A CMOS image sensor comprising:
a lower semiconductor chip; and
an upper semiconductor chip mounted on the upper semiconductor chip,
wherein the upper semiconductor chip comprises
an array of pixels, each pixel comprising a photodiode positioned to receive light from a light source external to the CMOS image sensor and connected to a source follower transistor, the source follower transistor configured to provide an analog pixel signal corresponding to a charge accumulated by the corresponding photodiode,
a plurality of column signal lines, each column signal line connected to a column of pixels to receive corresponding analog pixel signals, and
a plurality of row lines, each row line connected to a corresponding row of pixels to connect each of the pixels of the row of pixels to a corresponding source follower transistor to provide the corresponding analog pixel signal to the corresponding column signal line,

wherein the lower semiconductor chip comprises
a logic region having arranged therein logic circuits including an analog to digital converter configured to provide digital pixel data correlated to analog pixel signals provided by the plurality of column signal lines, and
a memory region, having embedded therein a magnetic random access memory (MRAM) configured to receive and store image frame data resulting from the digital pixel data provide by the analog to digital converter,

wherein the MRAM comprises unit cells including cell transistors and magnetic tunnel junction (MTJ) structures, the unit cells being arranged in the memory region in a two-dimensional array structure,
wherein the cell transistors are arranged on the same level as transistors of the logic region,
wherein each MTJ structure comprises a pinned layer, a tunnel layer, and a free layer,
wherein each MTJ structure is positioned between two wire layers adjacent to each other from among a plurality of wire layers arranged above the cell transistors, and
wherein the MTJ structures are positioned between a wire layer forming a plurality of bit lines and a wire layer connected to drain regions o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dae-Shik
• Koh Gwan-Hyeob

Classifications

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H04N23/12

  with one sensor only · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/447

  by preserving the colour pattern with or without loss of information · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title