Interface for parallel configuration of programmable devices

Patent metadata

Field	Value
Publication number	US-2019103872-A1
Application number	US-201816146849-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 4, 2019
Grant date	—

Abstract

An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a first integrated circuit die comprising first circuitry that comprises a memory, a register, or both, and a first controller for a microbump interface; and a second integrated circuit die comprising a second controller for the microbump interface, wherein the first controller and the second controller are coupled via a control interface that comprises a microbump connection.

2 . The integrated circuit device of claim 1 , wherein the first integrated circuit die comprises a data register configured to couple the microbump interface and the first circuitry.

3 . The integrated circuit device of claim 2 , wherein the memory comprises a plurality of memory columns, wherein the data register comprises a plurality of memory controllers, and wherein the first controller is configured to control the plurality of memory controllers.

4 . The integrated circuit device of claim 3 , wherein the memory comprises an embedded random-access memory (ERAM).

5 . The integrated circuit device of claim 2 , wherein the first integrated circuit die comprises programmable logic, the memory comprises configuration memory that controls the programmable logic, and the microbump interface is configured to transport configuration data from the second integrated circuit die to the first integrated circuit die or from the first integrated circuit die to the second integrated circuit die.

6 . The integrated circuit device of claim 5 , wherein the configuration memory comprises a plurality of memory segments, and wherein the data register is configured to load the configuration data employing pipelining.

7 . The integrated circuit device of claim 5 , wherein the second integrated circuit die comprises a network on chip (NOC) circuitry, and wherein the configuration data is received from the NOC circuitry.

8 . The integrated circuit device of claim 5 , wherein the second integrated circuit die comprises a second memory that comprises the configuration data.

9 . The integrated circuit device of claim 2 , wherein the second integrated circuit die comprises testing circuitry, and wherein the data register is configured to load test data into a scan chain that comprises the register and to retrieve return data from the scan chain to the testing circuitry.

10 . The integrated circuit device of claim 9 , wherein the testing circuitry comprises a linear feedback shift register (LFSR) checker.

11 . The integrated circuit device of claim 9 , wherein the testing circuitry comprises a test pattern generator that generates the test data.

12 . The integrated circuit device of claim 11 , wherein the test pattern generator comprises a linear feedback shift register (LFSR) generator.

13 . The integrated circuit device of claim 1 , comprising a third integrated circuit die coupled to the second integrated circuit die via a second microbump interface, wherein the third integrated circuit die comprises second circuitry that comprises a second memory or a second register or both, and a third controller for the second microbump interface, and wherein the second integrated circuit die comprises a fourth controller for the second microbump interface that is coupled to the third controller via a second control interface that comprises a second microbump connection.

14 . A method to program a programmable logic device, comprising:
sending a write request from a first controller of a microbump interface disposed in a fabric die to a second controller of the microbump interface disposed in a base die using a first control interface that comprises a microbump connection, wherein the fabric die and the base die are coupled via the microbump interface; transmitting a first portion of configuration data from a memory in the base die to a data register in the fabric die using the microbump interface, wherein the microbump interface comprises a plurality of channels; and loading the first portion of the configuration data from the data register to a configuration memory of the fabric die.

15 . The method of claim 14 , wherein loading the first portion of configuration data from the data register to the configuration memory comprises:
storing the first portion of the configuration data received from the microbump interface in a first segment of the data register; copying the first portion of the configuration data from the first segment of the data register to a second segment of the data register; and transferring the first portion of the configuration data from the second segment of the data register to the configuration memory.

16 . The method of claim 14 , wherein the configuration memory comprises a plurality of pipeline segments, and wherein loading the first portion of the configuration data comprises:
loading the first portion of the configuration data in a first pipeline segment of the memory; and simultaneously shifting the first portion of the configuration data in the first pipeline segment of the memory to a second pipeline segment of the memory and storing a second portion of the configuration data in the first pipeline segment of the memory.

17 . The method of claim 14 , wherein the base die comprises network on chip (NOC) circuitry, and wherein the method comprises:
receiving, in the base die, the first portion of configuration data via the NOC circuitry; and storing the first portion of configuration data in the memory in the base die.

18 . The method of claim 14 , comprising:
receiving, in the first controller, a legacy write request from a sector controller of the fabric die; and generating, in the first controller, the write request based, in part, on the legacy write request.

19 . The method of claim 14 , comprising transmitting a second portion of the configuration data from the memory in the base die to the data register in the fabric die using the microbump interface while loading the first portion of configuration data from the data register to the configuration memory of the fabric die.

20 . The method of claim 19 , wherein the plurality of channels comprises a first bandwidth, the data register comprises a second bandwidth, and wherein transmitting the first portion of configuration data comprises receiving the first portion of configuration data in the first interface at a first frequency and the first bandwidth and providing the first portion of configuration data from the first interface to the data register at a second frequency and the second bandwidth.

21 . An electronic device, comprising:
a fabric die that comprises:
programmable fabric;
configuration memory configured to program the programmable fabric; and
a first controller for a microbump interface; and
a base die coupled to the fabric die via the microbump interface, comprising a second controller for the microbump interface coupled to the first controller via a microbump connection, wherein the first controller and the second controller are configured to control exchange of configuration data between the base die and the configuration memory via the microbump interface.

22 . The electronic device of claim 21 , wherein the fabric die comprises user memory, and wherein the first controller and the second controller are configured to control exchange of user data between the base die and the user memory via the microbump interface.

23 . The electronic device of claim 21 , comprising a data processing system c

Assignees

• Intel Corp

Inventors

• Clark Kevin
• Weber Scott J
• Ball James
• Chong Simon
• Gutala Ravi Prakash
• Dasu Aravind Raghavendra

Classifications

• H03K19/17758

  for speeding up configuration or reconfiguration · CPC title

• H03K19/17708

  using an AND matrix followed by an OR matrix, i.e. programmable logic arrays · CPC title

• H03K19/17768

  for security · CPC title

• H03K19/1776 Primary

  for memories · CPC title

• H03K19/17776

  Electricity · mapped topic