Hardmask stress, grain, and structure engineering for advanced memory applications
US-2020126791-A1 · Apr 23, 2020 · US
Resistive memory crossbar array with a multilayer hardmask
US10833268B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10833268-B2 |
| Application number | US-201916287485-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 27, 2019 |
| Priority date | Feb 27, 2019 |
| Publication date | Nov 10, 2020 |
| Grant date | Nov 10, 2020 |
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Abstract
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Devices and/or methods that facilitate forming a resistive memory crossbar array with a multilayer hardmask are provided. In some embodiments, a resistive random access memory (RRAM) can comprise a multilayer hardmask comprising three layers, an interlayer oxide between a first layer of silicon nitride and a second layer of silicon nitride. In other embodiments, an RRAM can comprise a multilayer hardmask comprising two layers, a layer of an oxide on a layer of silicon nitride.
First claim
Opening claim text (preview).
What is claimed is: 1. A device, comprising: a resistive random access memory (RRAM) comprising a multilayer hardmask, wherein the multilayer hardmask comprises an interlayer oxide, and wherein the multilayer hardmask comprises a first layer of silicon nitride and a second layer of silicon nitride, and wherein the interlayer oxide is between the first layer of silicon nitride and the second layer of silicon nitride. 2. The device of claim 1 , wherein the RRAM comprises a first electrode layer selected from a group consisting of titanium nitride, tantalum nitride and tungsten. 3. The device of claim 1 , wherein the RRAM comprises a metal oxide selected from a group consisting of halfnium oxide, tantalum oxide, titanium oxide and aluminum oxide. 4. The device of claim 1 , wherein the RRAM comprises a second electrode layer selected from a group consisting of titanium, titanium nitride and a combination of titanium and titanium nitride. 5. The device of claim 1 , wherein the multilayer hardmask comprises two layers, and wherein the two layers comprises the interlayer oxide on the first layer of silicon nitride. 6. The device of claim 1 , wherein the interlayer oxide causes a surface oxidation of the first layer of silicon nitride. 7. The device of claim 1 , wherein the interlayer oxide comprises an oxide, and wherein the oxide comprises silicon oxide or silicon oxynitride. 8. A method, comprising: forming a resistive random access memory (RRAM) comprising a multilayer hardmask, wherein the multilayer hardmask comprises an interlayer oxide, and wherein the multilayer hardmask comprises a first layer of silicon nitride and a second layer of silicon nitride, and wherein the interlayer oxide is between the first layer of silicon nitride and the second layer of silicon nitride. 9. The method of claim 8 , further comprising building the RRAM between copper lines. 10. The method of claim 8 , wherein the RRAM comprises a first electrode layer selected from a group consisting of titanium nitride, tantalum nitride and tungsten. 11. The method of claim 8 , wherein the RRAM comprises a metal oxide selected from a group consisting of halfnium oxide, tantalum oxide, titanium oxide and aluminum oxide. 12. The method of claim 8 , wherein the RRAM comprises a second electrode layer selected from a group consisting of titanium, titanium nitride and a combination of titanium and titanium nitride. 13. The method of claim 8 , further comprising removing the second layer of silicon nitride. 14. The method of claim 8 , wherein the multilayer hardmask comprises two layers, and wherein the two layers comprises the interlayer oxide on the first layer of silicon nitride. 15. The device of claim 8 , wherein the interlayer oxide comprises an oxide, and wherein the oxide comprises silicon oxide or silicon oxynitride. 16. A device, comprising: a resistive random access memory (RRAM) comprising a multilayer hardmask, wherein the multilayer hardmask comprises a first layer of an oxide on a first layer of silicon nitride, and wherein the multilayer hardmask comprises a second layer of silicon nitride, and wherein the layer of an oxide is between the first layer of silicon nitride and the second layer of silicon nitride.
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L45/1675Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US10833268B2 cover?
- Devices and/or methods that facilitate forming a resistive memory crossbar array with a multilayer hardmask are provided. In some embodiments, a resistive random access memory (RRAM) can comprise a multilayer hardmask comprising three layers, an interlayer oxide between a first layer of silicon nitride and a second layer of silicon nitride. In other embodiments, an RRAM can comprise a multilaye…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L45/1675. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 10 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).