MRAM etching processes

Patent metadata

Field	Value
Publication number	US-8975088-B2
Application number	US-201313954673-A
Country	US
Kind code	B2
Filing date	Jul 30, 2013
Priority date	Aug 30, 2011
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

First claim

The invention claimed is:

1. A method of fabricating a memory cell comprising:
depositing a stack of layers for a memory device including a memory element and a bottom electrode;
depositing a top electrode layer;
depositing a hard mask buffer layer over the top electrode layer;
depositing a hard mask layer over the hard mask buffer layer;
patterning a photoresist pad on a selected location on the hard mask layer leaving an exposed area;
performing a first etching process that completely removes the exposed area of the hard mask layer and partially removes the hard mask buffer layer under the hard mask layer without exposing the top electrode layer; and
performing a second etching process that removes the exposed area of the hard mask buffer layer and the top electrode layer using a selected etching ambient.

2. The method of claim 1 wherein the hard mask buffer layer is silicon nitride.

3. The method of claim 1 wherein the hard mask buffer layer is silicon carbide.

4. The method of claim 1 wherein the top electrode layer is tantalum.

5. The method of claim 1 wherein the top electrode layer is tantalum nitride.

6. The method of claim 1 wherein the first etching process continues until approximately one half of a thickness of the hard mask buffer layer has been removed.

7. The method of claim 1 wherein the hard mask buffer layer is silicon nitride; the top electrode layer is tantalum and the selected etching ambient is CF4, CH3F, CF4/O2 or Cl2/BCl3.

8. The method of claim 1 wherein the hard mask buffer layer is silicon carbide;
the top electrode layer is tantalum and the selected etching ambient is CF4, CH3F, CF4/O2 or Cl2/BCl3.

9. The method of claim 1 wherein depositing the top electrode layer further comprises:
depositing a first top electrode layer of copper on an upper layer of the memory element; and
depositing a second top electrode layer of a selected metal other than copper on the first top electrode layer.

Assignees

• Avalanche Technology Inc
• Avalanche Technology Inc

Inventors

• Satoh Kimihiro
• Huai Yiming
• Zhang Jing
• Ranjan Rajiv Yadav
• Keshtbod Parviz
• Malmhall Roger K

Classifications

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H01L29/00

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H10N50/01 Primary

  Manufacture or treatment · CPC title