Method for producing a memory cell having a porous dielectric and use of the memory cell

US10833264B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10833264-B2
Application numberUS-201716078655-A
CountryUS
Kind codeB2
Filing dateMar 8, 2017
Priority dateMar 23, 2016
Publication dateNov 10, 2020
Grant dateNov 10, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for producing a memory cell includes providing a non-conductive substrate, mounting a first conductor track made of conductive material on the non-conductive substrate, mounting a porous dielectric with or without redox-active molecules in a form of points on the first conductor track, and mounting a second conductor track orthogonally to the first conductor track, wherein the first and second conductor tracks have an electrode function at their intersection point, and wherein the porous dielectric is arranged between the electrodes. The method further includes mounting a passivation layer on the substrate, the first conductor track, the dielectric, and the second conductor track, so that the conductor track remains contactable. The first and the second conductor track form a memory at their intersection point with the dielectric arranged between them, in which the redox reaction of the redox-active molecules is configured to be driven by a voltage.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for producing a memory cell, the method comprising: a) providing a non-conductive substrate; b) mounting a first conductor track on the non-conductive substrate; c) mounting a porous dielectric with redox-active molecules at an intersection point on the first conductor track such that the porous dielectric contacts a top side of the first conductor track at the intersection point, wherein the porous dielectric is a sol-gel ink or a hydrogel ink that is dried after being mounted on the first conductor track so as to form a nanoporous layer comprising pores having a residual liquid volume that includes the redox-active molecules; d) mounting a second conductor track orthogonally to the first conductor track such that the second conductor track contacts a top side of the porous dielectric at the intersection point; and e) mounting, in a manner such that the first and second conductor tracks remain contactable, a passivation layer on the substrate, the first conductor track, the porous dielectric, and the second conductor track; wherein the first conductor track forms a first electrode at the intersection point and the second conductor track forms a second electrode at the intersection point, wherein the first conductor track, the porous dielectric, and the second conductor track are configured to form a memory state at the intersection point, and wherein the first and second conductor tracks are configured to apply a voltage between the first and second electrodes so as to drive a redox reaction of the redox-active molecules in order to generate the memory state. 2. The method as claimed in claim 1 , wherein the first conductor track and/or the porous dielectric and/or the second conductor track and/or the passivation layer are mounted by a printing method. 3. The method as claimed in claim 1 , wherein the sol-gel ink or the hydrogel ink includes the redox-active molecules, and wherein the redox-active molecules are configured to diffuse into the pores of the porous dielectric and become transformed at the first and second electrodes. 4. The method as claimed in claim 1 , further comprising mounting a plurality of additional first conductor tracks arranged orthogonally to the second conductor track, mounting additional porous dielectrics at additional intersection points on the first conductor track or on the additional first conductor tracks, and mounting a plurality of additional second conductor tracks arranged orthogonally to the first conductor track such that the plurality of additional second conductor tracks contact a top side of the additional porous dielectrics at the plurality of additional intersection points in order to form a storage array. 5. The method as claimed in claim 4 , wherein the additional porous dielectrics include redox-active molecules of inks with different concentrations and/or substances. 6. The method as claimed in claim 1 , wherein the porous dielectric includes residual liquid, and wherein the redox-active molecules are configured to be transported to the first and second electrodes by diffusion in the residual liquid. 7. A memory cell, comprising: a non-conducting substrate; a first electrically contactable conductor track disposed on the non-conducting substrate; a porous dielectric including residual liquid and redox-active molecules freely diffusible into pores, the porous dielectric being disposed at an intersection point on the first electrically contactable conductor track such that the porous dielectric contacts a top side of the first electrically contactable conductor track; and a second electrically contactable conductor track arranged orthogonally to the first electrically contactable conductor track and further arranged so as to contact a top side of the porous dielectric at the intersection point, wherein the first electrically contactable conductor track forms a first electrode at the intersection point and the second electrically contactable conductor track forms a second electrode at the intersection point, wherein the first and second electrically contactable conductor tracks are configured to apply a voltage between the first and second electrodes so as to oxidize and/or reduce the redox-active molecules in the porous dielectric in order to create storage states, wherein the redox-active molecules are configured to be transported to the first and second electrodes by diffusion in the residual liquid, and wherein the memory cell is completely passivated by a passivation layer. 8. A storage array having a plurality of memory cells as claimed in claim 7 in a “crossbar” configuration. 9. The storage array as claimed in claim 8 , wherein different memory cells of the storage array comprise several different redox-active molecules and/or different concentrations of a redox-active molecule. 10. The storage array as claimed in claim 8 , wherein the storage array is a read-only memory (ROM) storage array comprising a plurality of nanoporous dielectrics without redox-active molecules and a plurality of nanoporous dielectrics with a redox-active molecule, wherein the redox-active molecule is configured to be reversibly oxidized and reduced solely between its two oxidation states according to a reaction A↔B. 11. The storage array as claimed in claim 8 , wherein the storage array is a write once, read many memory (WORM) storage array comprising a plurality of nanoporous dielectrics with a redox-active molecule, wherein the redox-active molecule is configured to be reversibly oxidized and reduced between its two oxidation states A and B according to a first reaction A↔B, and wherein the redox-active molecule additionally has at least one further irreversible oxidation state according to a second irreversible reaction B→C and/or a third irreversible reaction A→D. 12. The storage array as claimed in claim 8 , wherein the storage array is a rewritable memory (RW) storage array comprising a plurality of nanoporous dielectrics with a redox-active molecule, wherein the redox-active molecule is configured to be reversibly oxidized and reduced between its two oxidation states A and B according to a first reaction A↔B, and wherein the redox-active molecule additionally has at least one further reversible oxidation state according to a second reversible reaction B↔C and/or a third reversible reaction A↔D. 13. The ROM storage array as claimed in claim 10 , wherein the redox-active molecule is configured to be reversibly oxidized and reduced according to the reaction A↔B by applying voltage to the first and second electrodes with a read out potential above and below the normal potential of the redox-active molecule and the current measured upon passing a threshold value is read out as the state “1” and wherein the state 0 is read out for memory cells without redox-active molecules. 14. The WORM storage array as claimed in claim 11 , wherein the redox-active molecule is configured to be reversibly oxidized and reduced according to the reaction A↔B by applying voltage to the first and second electrodes with a read out potential above and below the normal potential of the redox-active molecule and the current measured upon passing a threshold value is read out as the state 1. 15. The WORM storage array as claimed in claim 14 , wherein the redox-active molecule is configured to be rewritten into the irreversible oxidation state according to the reaction B→C or A→D by applying voltage to the first and second electrodes with a writing potential, so that the redox-active molecule is no longer oxidized or reduced according to the reaction A↔B by applying vo

Assignees

Inventors

Classifications

  • using elements whose operation depends upon chemical change {(G11C13/0009 takes precedence)} · CPC title

  • using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

  • Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

  • Integrated devices comprising a common active layer · CPC title

  • Electrodes · CPC title

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What does patent US10833264B2 cover?
A method for producing a memory cell includes providing a non-conductive substrate, mounting a first conductor track made of conductive material on the non-conductive substrate, mounting a porous dielectric with or without redox-active molecules in a form of points on the first conductor track, and mounting a second conductor track orthogonally to the first conductor track, wherein the first an…
Who is the assignee on this patent?
Forschungszentrum Juelich Gmbh
What technology area does this patent fall under?
Primary CPC classification G11C13/004. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 10 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).