Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10833041-B2
Application number	US-201715828948-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	Jul 31, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A fan-out semiconductor package may include a support member having a through-hole, a semiconductor chip disposed in the through-hole, a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip in the through-hole by a predetermined distance, an encapsulant, and a connection member. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. The component embedded structure has a plurality of passive components embedded therein. The encapsulant encapsulates at least portions of the support member, the component embedded structure, and the semiconductor chip. The connection member is disposed on the support member, the component embedded structure, and the active surface of the semiconductor chip. The connection member includes redistribution layers and vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads of the semiconductor chip.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a semiconductor chip comprising:
an active surface having connection pads disposed thereon; and
an inactive surface opposing the active surface;

a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip by a predetermined distance, the component embedded structure comprising:
a substrate, the substrate comprising a cavity;
a plurality of passive components disposed in the cavity, each passive component of the plurality of passive components comprising electrodes that cover an entirety of vertical sidewalls of the respective passive components; and
a resin layer covering the plurality of passive components and the electrodes within the cavity such that the resin directly contacts respective top surfaces of the electrodes adjacent to a top surface of the respective passive components;

an encapsulant encapsulating at least portions of the component embedded structure and the semiconductor chip; and
a connection member disposed on the component embedded structure, and the active surface of the semiconductor chip, wherein the connection member includes:
redistribution layers; and
vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads of the semiconductor chip.

2. The fan-out semiconductor package of claim 1 , wherein:
lower surfaces of the electrodes of the plurality of passive components are exposed from a lower surface of the resin layer to be connected to the vias of the connection member.

3. The fan-out semiconductor package of claim 2 , wherein outer surfaces of the component embedded structure except for a lower surface of the component embedded structure are covered with a metal layer.

4. The fan-out semiconductor package of claim 3 , wherein the metal layer is connected to ground patterns of the redistribution layers of the connection member.

5. The fan-out semiconductor package of claim 1 , wherein:
the component embedded structure includes a first component embedded structure and a second component embedded structure, the first component embedded structure and the second component embedded structure disposed adjacent to and spaced apart from each other by a predetermined distance, each of the first component embedded structure and the second component embedded structure having a plurality of passive components embedded therein, respectively, and
the semiconductor chip is disposed between the first component embedded structure and the second component embedded structure.

6. The fan-out semiconductor package of claim 5 , wherein outer surfaces of either of the first component embedded structure and the second component embedded structure except for a lower surface of any one of the first component embedded structure and the second component embedded structure are covered with a metal layer.

7. The fan-out semiconductor package of claim 6 , wherein the metal layer is connected to ground patterns of the redistribution layers of the connection member.

8. The fan-out semiconductor package of claim 6 , wherein:
the plurality of passive components embedded in the first component embedded structure include capacitors, and
the plurality of passive components embedded in the second component embedded structure include inductors.

9. The fan-out semiconductor package of claim 1 , wherein:
the fan-out semiconductor package further comprises a support member having a through-hole,
the semiconductor chip and the component embedded structure are disposed in the through hole,
the encapsulant encapsulates at least portions of the support member,
the connection member is disposed on the support member, and
the support member includes:
a first insulating layer;
a first redistribution layer in contact with the connection member and embedded in a first surface of the first insulating layer; and
a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface, and

the first redistribution layer and the second redistribution layer are electrically connected to the connection pads of the semiconductor chip.

10. The fan-out semiconductor package of claim 9 , wherein:
the support member further includes:
a second insulating layer disposed on the first insulating layer and covering the second redistribution layer; and
a third redistribution layer disposed on the second insulating layer, and

the third redistribution layer is electrically connected to the connection pads of the semiconductor chip.

11. The fan-out semiconductor package of claim 9 , wherein a distance between the redistribution layers of the connection member and the first redistribution layer is greater than that between the redistribution layers of the connection member and a connection pad of the connection pads of the semiconductor chip.

12. The fan-out semiconductor package of claim 1 , wherein the fan-out semiconductor package further comprises a support member having a through-hole,
the semiconductor chip and the component embedded structure are disposed in the through hole,
the encapsulant encapsulates at least portions of the support member,
the connection member is disposed on the support member, and
the support member includes a first insulating layer, a first redistribution layer disposed on a lower surface of the first insulating layer, and a second redistribution layer disposed on an upper surface of the first insulating layer, and
the first redistribution layer and the second redistribution layer are electrically connected to the connection pads of the semiconductor chip.

13. The fan-out semiconductor package of claim 12 , wherein the support member further includes a second insulating layer disposed on the first insulating layer and covering the first redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the connection pads of the semiconductor chip.

14. The fan-out semiconductor package of claim 13 , wherein the support member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the connection pads of the semiconductor chip.

15. The fan-out semiconductor package of claim 13 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Jun Oh
• Sung Ki Jung

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title