Semiconductor memory systems with on-die data buffering

Patent metadata

Field	Value
Publication number	US-10831685-B2
Application number	US-201916546694-A
Country	US
Kind code	B2
Filing date	Aug 21, 2019
Priority date	Oct 16, 2012
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

First claim

What is claimed is:

1. A DRAM integrated circuit (IC) chip comprising:
DRAM storage cells formed on the DRAM IC chip;
a primary interface formed on the DRAM IC chip for transferring data signals with a first IC chip;
a secondary interface formed on the DRAM IC chip for transferring the data signals with a second DRAM IC chip;
a command/address (C/A) interface formed on the DRAM chip for transferring C/A signals directly with the first IC chip via a C/A signal path, the C/A signal path directly coupling the first IC chip with the second DRAM IC chip;
configuration circuitry for configuring use of the secondary interface between a first mode of operation and a second mode of operation; and
wherein the C/A interface receives the C/A signals from the DRAM IC chip for both the first and second modes of operation.

2. The DRAM IC chip according to claim 1 , wherein the configuration circuitry configures use of the secondary interface to retransmit write data in the first mode of operation.

3. The DRAM IC chip according to claim 2 , further comprising:
buffer circuitry coupled to the secondary interface, the buffer circuitry to, in the first mode of operation, retransmit the write data received by the primary interface to the second DRAM IC chip via the secondary interface.

4. The DRAM IC chip according to claim 3 , wherein the first IC chip comprises a memory controller IC chip.

5. The DRAM IC chip according to claim 1 , wherein the configuration circuitry configures use of the secondary interface to receive write data in the second mode of operation.

6. The DRAM IC chip according to claim 3 , wherein:
the DRAM storage cells include memory core circuitry coupled to the primary interface, the memory core circuitry to transfer signals with the first IC chip via the primary interface.

7. The DRAM IC chip according to claim 6 , wherein the first IC chip is embodied as a memory controller chip.

8. A dynamic random access memory (DRAM) chip package, comprising:
multiple DRAM integrated circuit (IC) chips disposed in a stacked relationship, each of the multiple DRAM IC chips comprising
a primary interface for transferring data signals with a logic IC chip;
a secondary interface for transferring the data signals with at least one of the other DRAM IC chips;
a command/address (C/A) interface for transferring C/A signals directly with the logic IC chip via a C/A signal path, the C/A signal path directly coupling the logic IC chip with the at least one of the other DRAM IC chips;
configuration circuitry for configuring use of the secondary interface between a first mode of operation and a second mode of operation; and
wherein the C/A interface receives the C/A signals from the logic IC chip for both the first and second modes of operation.

9. The DRAM chip package according to claim 8 , wherein the configuration circuitry configures use of the secondary interface to retransmit write data in the first mode of operation.

10. The DRAM chip package according to claim 8 , wherein each of the multiple DRAM IC chips further comprises:
buffer circuitry coupled to the secondary interface, the buffer circuitry to, in the first mode of operation, retransmit the write data received by the primary interface to the at least one of the other DRAM IC chips via the secondary interface.

11. The DRAM chip package according to claim 10 , wherein:
the logic IC chip comprises a memory controller IC chip.

12. The DRAM chip package according to claim 8 , wherein:
the configuration circuitry configures use of the secondary interface to receive write data in the second mode of operation.

13. The DRAM chip package according to claim 10 , wherein:
each of multiple DRAM IC chips include memory core circuitry coupled to the primary interface, the memory core circuitry to transfer signals with the logic IC chip via the primary interface.

14. The DRAM IC chip according to claim 13 , wherein:
the logic IC chip comprises a memory controller IC chip.

15. A method of operation in a dynamic random access memory (DRAM) integrated circuit (IC) chip, the method comprising:
selectively transferring data signals with a second IC chip via a primary interface formed on the DRAM IC chip;
transferring signals with a second DRAM IC chip via a secondary interface formed on the DRAM IC chip;
transferring command/address (C/A) signals directly with the second IC chip via a C/A signal path, the C/A signal path directly coupling the second IC chip with the second DRAM IC chip;
configuring use of the secondary interface between a first mode of operation and a second mode of operation with configuration circuitry; and
wherein the C/A interface receives the C/A signals from the second IC chip for both the first and second modes of operation.

16. The method according to claim 15 , wherein the configuring use comprises:
configuring use of the secondary interface in a retransmit mode or a write data receive mode.

17. The method according to claim 16 , further comprising:
in the retransmit mode, retransmitting signals received by the primary interface to the second DRAM IC chip via the secondary interface.

18. The method according to claim 16 , further comprising:
transferring signals with the second IC chip via the primary interface when the secondary interface is configured in the retransmit mode.

19. The method according to claim 18 , wherein the second IC chip is embodied as a memory controller IC chip.

20. The method according to claim 15 , wherein:
the configuring use of the secondary interface is carried out in response to a control signal.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Amirkhany Amir
• Rajan Suresh
• Hekmat Mohammad
• Patil Dinesh

Classifications

• G11C7/1087

  Data input latches · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title