Ensuring completeness of interface signal checking in functional verification

Patent metadata

Field	Value
Publication number	US-10830818-B2
Application number	US-201715714071-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 25, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.

First claim

What is claimed is:

1. A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:
performing, a static source code analysis of a verification software source code, resulting in a list of interface signals to be verified in a checker control flow database;
adding an attribute value and code to an interface signal variable in the verification software source code, resulting in instrumented verification software source code;
executing the instrumented verification software source code against a chip design, resulting in a trace file;
determining, from the trace file, occurrences of accesses to the interface signal variable;
analyzing the checker control flow database and creating a logical connection to a second checker control flow database based on a second attribute value in the second database;
generating a signal checker coverage report linking hardware signals for the chip design, control variables associated with the hardware signals, and a coverage hole report,
wherein the coverage hole report indicates whether the interface signal variable has not been issued by the chip design under test, according to the verification software source code; and

matching the occurrences with the checker control flow database, resulting in a list of interface signal variables that have not been checked by executing the verification software source code.

2. The computer program product of claim 1 , wherein the method further comprises:
creating a checker dependency network by extracting names of verification end nodes from a checker database;
correlating the verification end nodes;
collecting weight attributes;
associating the weight attributes to the correlations;
grouping one or more checkers based on the correlations and weight attributes; and
visually reporting the grouping.

3. The computer program product of claim 1 , wherein the method further comprises:
tracing a function call of an instrumented comparison method, the instrumented comparison method overwriting an original comparison method and adding a write statement for a trace output,
wherein the second attribute is added to an attribute list of assigned attributed variables; and

instrumenting the verification software source by inserting one or more logical operations between the attributed variables.

4. A computer implemented method comprising:
performing, by a computer system, a static source code analysis of a verification software source code, resulting in a list of interface signals to be verified in a checker control flow database;
adding a color and a code to an interface signal variable in the verification software source code, resulting in an instrumented verification software source code;
executing the instrumented verification software source code, against a chip design, resulting in a trace file;
determining, from the trace file, occurrences of accesses to the interface signal variable;
analyzing the checker control flow database and creating a logical connection to a second checker control flow database based on a second attribute value in the second database;
generating a signal checker coverage report linking hardware signals, control variables associated with the hardware signals, and a coverage hole report,
wherein the coverage hole report indicates whether the interface signal variable has not been issued by the chip design under test, according to the verification software source code; and

matching the occurrences with the checker control flow database, resulting in a list of interface signal variables that have not been checked by executing the verification software source code.

5. The method of claim 4 , further comprising displaying, based on the matching, occurrences of colors from the instrumented verification software source code, along with a signal variable names corresponding to the colors, and a verification end node name resulting in a digest concerning a test coverage.

6. The method of claim 5 further comprising, creating, by the computer system, a control flow graph of the verification software source code.

7. The method of claim 4 , wherein the attribute value is binary hash value of a name of the interface signal variable.

Assignees

• IBM

Inventors

• Greiner Carsten
• Tran Minh Cuong
• Koch Gerrit
• Walter Joerg

Classifications

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G01R31/318307

  computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title

• G01R31/318357 Primary

  Simulation (computer simulation of digital circuits G06F30/3308) · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title