Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
US9286426B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9286426-B2 |
| Application number | US-201414259163-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 23, 2014 |
| Priority date | Apr 23, 2014 |
| Publication date | Mar 15, 2016 |
| Grant date | Mar 15, 2016 |
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A computer-implemented method, apparatus and computer program product for testing a design, the method comprising receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; translating the scenario to an input for a verification engine, wherein the verification engine is selected from the group consisting of a simulation engine and a formal analysis engine; activating the engine and providing the input to the engine, whereby the engine outputting a result; and displaying the result.
Opening claim text (preview).
What is claimed is: 1. A computer-implemented method performed by a computerized device, comprising: receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; selecting whether a verification engine to be used is a simulation engine or a formal analysis engine; translating the scenario to an input for the verification engine as selected; activating the verification engine as selected, and providing the input to the verification engine, whereby the verification engine outputting a result; and displaying the result. 2. The method of claim 1 , wherein said receiving the description of the scenario and said displaying the results utilize a single user interface having at least an input area and an output area. 3. The method of claim 1 , wherein the scenario comprises values of an input signal at different cycles. 4. The method of claim 1 wherein the scenario is entered using a spreadsheet-like interface. 5. The method of claim 4 wherein a signal is described by drawing horizontal lines in one or more cells in a spreadsheet using a pointing device. 6. The method of claim 5 , wherein the spreadsheet-like interface provides for adding at least one graphical element to the wave form signal description. 7. The method of claim 5 wherein a value in the spreadsheet is interpreted in at least two manners based upon the at least one graphical element. 8. The method of claim 4 wherein the spreadsheet-like interface provides an element representing repeating a part of the signal multiple times. 9. The method of claim 4 wherein the spreadsheet-like interface provides an element representing delaying a part of the signal for one or more cycles. 10. The method of claim 4 wherein the spreadsheet-like interface provides for using a macro for entering a scenario. 11. The method of claim 1 wherein the scenario is defined based on two or more signals, wherein the scenario defines that the two or more signals are synchronized. 12. The method of claim 1 , wherein a feature of the scenario is automatically translated into a coverage goal for the simulation engine and into an exploration goal for the formal analysis engine. 13. The method of claim 1 , wherein correctness checker is generated for checking an expected result of the scenario. 14. A computerized apparatus having a processor, the processor being adapted to perform the steps of: receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; selecting whether a verification engine to be used is a simulation engine or a formal analysis engine; translating the scenario to an input for the verification engine as selected; activating the verification engine and providing the input to the verification engine, whereby the verification engine outputting a result; and displaying the result. 15. The computerized apparatus of claim 14 , comprising a spreadsheet-like interface for entering input comprising a signal, and receiving output. 16. The computerized apparatus of claim 15 wherein the signal is entered as horizontal lines in one or more cells in a spreadsheet. 17. The computerized apparatus of claim 15 wherein the spreadsheet-like interface provides for using a macro for entering a scenario. 18. A computer program product comprising a non-transitory computer readable storage medium retaining program instructions, which program instructions when read by a processor, cause the processor to perform a method comprising: receiving a design; receiving a description of a scenario, wherein the scenario relates to execution of the design, wherein the scenario is used for verifying the design; selecting whether a verification engine to be used is a simulation engine or a formal analysis engine; translating the scenario to an input for the verification engine as selected; activating the verification engine and providing the input to the verification engine, whereby the verification engine outputting a result; and displaying the result.
using formal methods, e.g. equivalence checking or property checking · CPC title
Design verification, e.g. functional simulation or model checking · CPC title
Circuit design · CPC title
Physics · mapped topic
Physics · mapped topic
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