Reduction of insertion loss in printed circuit board signal traces

Patent metadata

Field	Value
Publication number	US-10827627-B2
Application number	US-201916360216-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Mar 21, 2019
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A printed circuit board, according one embodiment, includes a reference layer; a dielectric layer disposed on the reference layer; and a conductor layer adhered to the dielectric layer with an adhesive layer disposed between the dielectric layer and the conductor layer. The conductor layer has a smooth surface facing the dielectric layer having a roughness (Rz) of less than two microns.

First claim

What is claimed is:

1. A multi-layer printed circuit board comprising:
a first core comprising a first reference layer and a first signal layer;
a first dielectric layer disposed on the first reference layer;
a first conductor layer adhered to the first dielectric layer with a first adhesive layer disposed between the first conductor layer and the first dielectric layer, wherein the first conductor layer has a smooth surface facing the first dielectric layer;
a second core comprising a second reference layer and a second signal layer;
a second dielectric layer disposed on the second reference layer; and
a second conductor layer adhered to the second dielectric layer with a second adhesive layer disposed between the second conductor layer and the second dielectric layer, wherein the second conductor layer has a smooth surface facing the second dielectric layer;
a third dielectric layer disposed between the first signal layer and the second signal layer;
a third adhesive layer disposed between the first reference layer and the first dielectric layer, wherein the first reference layer has a smooth surface facing the first dielectric layer; and
a fourth adhesive layer disposed between the first signal layer and the third dielectric layer, wherein the first signal layer has a smooth surface facing the third dielectric layer, and wherein each smooth surface has a roughness (Rz) of less than two microns.

2. The multi-layer printed circuit board of claim 1 , wherein the first conductor layer and the second conductor layer comprise copper foil.

3. The multi-layer printed circuit board of claim 1 , wherein the first signal layer and the second signal layer are etched to comprise a plurality of signal traces.

4. The multi-layer printed circuit board of claim 1 , wherein the first conductor layer is etched to comprise a plurality of signal traces, further comprising a first solder mask layer disposed on the etched first conductor layer.

5. The multi-layer printed circuit board of claim 1 , wherein the second conductor layer is etched to comprise a plurality of signal traces, further comprising a second solder mask layer disposed on the etched second conductor layer.

6. The multi-layer printed circuit board of claim 1 , wherein the first adhesive layer and the second adhesive layer each comprise a resin made of at least a perfluoroalkoxy copolymer.

7. The multi-layer printed circuit board of claim 1 , further comprising:
a fifth adhesive layer disposed between the second reference layer and the second dielectric layer, wherein the second reference layer has a smooth surface facing the second dielectric layer; and
a sixth adhesive layer disposed between the second signal layer and the third dielectric layer, wherein the second signal layer has a smooth surface facing the third dielectric layer.

Assignees

• Intel Corp

Inventors

• Ye Xiaoning
• Hsu Jimmy

Classifications

• H05K3/386 Primary

  by the use of an organic polymeric bonding layer, e.g. adhesive · CPC title

• H05K1/11 Primary

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K1/09

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K3/46

  Manufacturing multilayer circuits · CPC title